Method, apparatus, and system for improving reliability of data transmission involving an ethernet device

1. A data transmission method, comprising:

performing, by a physical medium attachment (PMA) layer of a PHY chip of an ethernet device, bit-level demultiplexing processing on y first data streams to obtain x second data streams, wherein the y first data streams are based on bit-level multiplexing processing, where x and y are positive integers, and x>y;

performing, by the PMA layer of the PHY chip of the ethernet device, block-level multiplexing processing on the x second data streams to obtain z third data streams, where z is a positive integer, x>z, and z≥1; and

outputting, by the PMA layer of the PHY chip of the ethernet device, the z third data streams over z output lanes.

2. The method according to claim 1 , wherein outputting the z third data streams over the z output lanes comprises:

mapping the z third data streams at a granularity of n bits to obtain x fifth data streams, mapping the x fifth data streams at a granularity of q bits to obtain s fourth data streams, and outputting the s fourth data streams over the output z lanes, wherein s and n are positive integers, q≥2, and n≥2; or

mapping the z third data streams at a granularity of n bits to obtain s fourth data streams, and outputting the s fourth data streams over the z output lanes, wherein s and n are positive integers, and n≥2.

3. The method according to claim 1 , wherein outputting the z third data streams over the z output lanes comprises:

mapping the z third data streams at a granularity of n bits to obtain x fifth data streams;

performing bit-level multiplexing processing on the x fifth data streams to obtain s fourth data streams; and

outputting the s fourth data streams over the z output lanes, wherein s and n are positive integers, and n≥2.

4. The method according to claim 1 , wherein the x second data streams comprise data of at least one forward error correction (FEC) codeword, and the method further comprises:

before performing block-level multiplexing processing on the x second data streams to obtain the z third data streams, performing FEC codeword error correction processing on the x second data streams to obtain x error-corrected second data streams.

5. The method according to claim 4 , wherein the x second data streams comprise data of a plurality of FEC codewords, and wherein before performing FEC codeword error correction processing on the x second data streams to obtain the x error-corrected second data streams, the method further comprises:

performing demapping processing on the x second data streams at a granularity of FEC symbols to obtain data expressed in FEC codewords; and

wherein performing FEC codeword error correction processing on the x second data streams to obtain the x error-corrected second data streams comprises:

performing FEC codeword error correction processing on data expressed in FEC codewords, to obtain error-corrected data; and

performing mapping processing on the error-corrected data at the granularity of FEC symbols to obtain the x error-corrected second data streams.

6. The method according to claim 1 , wherein z=1, and wherein performing block-level multiplexing processing on the x second data streams to obtain the z third data streams comprises:

sequentially multiplexing data of n consecutive bits obtained from each of the x second data streams according to a round robin sequence for the x second data streams, to obtain the third data stream, wherein n≥2.

7. The method according to claim 1 , wherein z≥2, x≥2, and performing block-level multiplexing processing on the x second data streams to obtain the z third data streams comprises:

sequentially multiplexing data of n consecutive bits obtained from each of the x second data streams to respective third data streams according to a round robin sequence for the x second data streams and the z third data streams until all data of the x second data streams is mapped to obtain the z third data streams, wherein n≥2.

8. The method according to claim 1 , wherein a granularity of the block-level multiplexing processing is a quantity of bits comprised in one forward error correction (FEC) symbol.

9. A data transmission method, comprising:

obtaining, by a physical medium attachment (PMA) layer of a PHY chip of an ethernet device, z third data streams over z input lanes, wherein the z third data streams are based on block-level multiplexing processing, where z is a positive integer, x>z, and z≥1;

performing, by the PMA layer of the PHY chip of the ethernet device, block-level demultiplexing processing on the z third data streams to obtain x second data streams; and

performing, by the PMA layer of the PHY chip of the ethernet device, bit-level multiplexing processing on the x second data streams to obtain y first data streams, where x and y are positive integers, and x>y.

10. The method according to claim 9 , wherein obtaining the z third data streams over the z input lanes comprises:

receiving s fourth data streams over the z input lanes, mapping the s fourth data streams at a granularity of q bits to obtain x fifth data streams, and mapping the x fifth data streams at a granularity of n bits to obtain the z third data streams, wherein s and n are positive integers, q≥2 , and n≥2; or

receiving s fourth data streams over the z input lanes, and mapping the s fourth data streams at a granularity of n bits to obtain the z third data streams, wherein s and n are positive integers, and n≥2.

11. The method according to claim 9 , wherein obtaining the z third data streams over the z input lanes comprises:

receiving s fourth data streams over the z input lanes, wherein s is a positive integer;

performing bit-level demultiplexing processing on the s fourth data streams to obtain x fifth data streams; and

performing block-level multiplexing processing on the x fifth data streams to obtain the z third data streams.

12. The method according to claim 9 , wherein the x second data streams comprise data of at least one forward error correction (FEC) codeword, and the method further comprises:

before performing bit-level multiplexing processing on the x second data streams to obtain they first data streams, performing FEC codeword error correction processing on the x second data streams to obtain x error-corrected second data streams.

13. The method according to claim 12 , wherein the x second data streams comprise data of a plurality of FEC codewords, and wherein before performing FEC codeword error correction processing on the x second data streams to obtain the x error-corrected second data streams, the method further comprises:

performing demapping processing on the x second data streams at a granularity of FEC symbols to obtain data expressed in FEC codewords; and

wherein performing FEC codeword error correction processing on the x second data streams to obtain the x error-corrected second data streams comprises:

performing FEC codeword error correction processing on data expressed in FEC codewords to obtain error-corrected data; and

performing mapping processing on the error-corrected data at the granularity of FEC symbols to obtain the x error-corrected second data streams.

14. The method according to claim 9 , wherein z=1, and wherein performing block-level demultiplexing processing on the z third data streams to obtain the x second data streams comprises:

sequentially demultiplexing data of n consecutive bits in the third data stream to obtain the x second data streams, wherein n≥2.

15. The method according to claim 9 , wherein z≥2, x≥2, and performing block-level demultiplexing processing on the z third data streams to obtain the x second data streams comprises:

sequentially demultiplexing data of n consecutive bits obtained from each of the z third data streams to respective second data streams according to a round robin sequence for the z third data streams and until all data of the z third data streams is mapped to obtain the x second data streams, wherein n≥2.

16. The method according to claim 9 , wherein a granularity of the block-level demultiplexing processing is a quantity of bits comprised in one FEC symbol.

17. An ethernet device, comprising:

a physical medium attachment (PMA) layer of a PHY chip, configured to:

perform bit-level demultiplexing processing on y first data streams to obtain x second data streams, wherein the y first data streams are based on bit-level multiplexing processing, where x and y are positive integers, and x>y; and

perform block-level multiplexing processing on the x second data streams to obtain z third data streams, where z is a positive integer, and x>z, and z≥1; and

an interface configured to

output the z third data streams over z output lanes.

18. The ethernet device according to claim 17 , wherein the interface is configured to:

map the z third data streams at a granularity of n bits to obtain x fifth data streams, map the x fifth data streams at a granularity of q bits to obtain s fourth data streams, and output the s fourth data streams over the z output lanes, wherein s and n are positive integers, q≥2, and n≥2; or

map the z third data streams at a granularity of n bits to obtain s fourth data streams, and output the s fourth data streams over the z output lanes, wherein s and n are positive integers, and n≥2.

19. The ethernet device according to claim 17 , wherein the interface is configured to:

map the z third data streams at a granularity of n bits to obtain x fifth data streams;

perform bit-level multiplexing processing on the x fifth data streams to obtain s fourth data streams; and

output the s fourth data streams over the z output lanes, wherein s and n are positive integers, and n≥2.

20. The ethernet device according to claim 17 , wherein the x second data streams comprise data of at least one forward error correction (FEC) codeword, and the PMA layer of the PHY chip is configured to:

before block-level multiplexing processing on the x second data streams to obtain the z third data streams, perform FEC codeword error correction processing on the x second data streams to obtain x error-corrected second data streams.

21. The ethernet device according to claim 17 , wherein z=1, and the PMA layer of the PHY chip is configured to:

sequentially multiplex data of n consecutive bits obtained from each of the x second data streams according to a round robin sequence for the x second data streams, to obtain the third data stream, wherein n≥2.

22. The ethernet device according to claim 17 , wherein z≥2, x≥2, and the PMA layer of the PHY chip is configured to:

sequentially multiplex data of n consecutive bits obtained from each of the x second data streams to respective third data streams according to a round robin sequence for the x second data streams and the z third data streams until all data of the x second data streams is mapped to obtain the z third data streams, wherein n≥2.

23. The ethernet device according to claim 17 , wherein a granularity of the block-level multiplexing processing is a quantity of bits comprised in one forward error correction (FEC) symbol.

24. An ethernet device, comprising:

an interface, configured to obtain z third data streams over z input lanes, wherein the z third data streams are based on block-level multiplexing processing, where z is a positive integer, x>z, and z≥1; and

a physical medium attachment (PMA) layer of a PHY chip, configured to:

perform block-level demultiplexing processing on the z third data streams to obtain x second data streams; and

perform bit-level multiplexing processing on the x second data streams to obtain y first data streams, where x and y are positive integers, and x>y.

25. The ethernet device according to claim 24 , wherein the interface is configured to:

receive s fourth data streams over the z input lanes, map the s fourth data streams at a granularity of q bits to obtain x fifth data streams, and map the x fifth data streams at a granularity of n bits to obtain the z third data streams, wherein s and n are positive integers, q≥2, and n≥2; or

receive s fourth data streams over the z input lanes, and map the s fourth data streams at a granularity of n bits to obtain the z third data streams, wherein s and n are positive integers, and n≥2.

26. The ethernet device according to claim 24 , wherein the interface is configured to:

receive s fourth data streams over the z input lanes, wherein s is a positive integer;

perform bit-level demultiplexing processing on the s fourth data streams to obtain x fifth data streams; and

perform block-level multiplexing processing on the x fifth data streams to obtain the z third data streams.

27. The ethernet device according to claim 24 , wherein the x second data streams comprise data of at least one forward error correction (FEC) codeword, and the PMA layer of the PHY chip is further configured to:

before performing bit-level multiplexing processing on the x second data streams to obtain the y first data streams, perform FEC codeword error correction processing on the x second data streams to obtain x error-corrected second data streams.

28. The ethernet device according to claim 24 , wherein z=1, and wherein the PMA layer of the PHY chip is configured to:

sequentially demultiplex data of n consecutive bits in the third data stream to obtain the x second data streams, wherein n≥2.

29. The ethernet device according to claim 24 , wherein z≥2, x≥2, and the PMA layer of the PHY chip is configured to:

sequentially demultiplex data of n consecutive bits obtained from each of the z third data streams to respective second data streams according to a round robin sequence for the z third data streams and until all data of the z third data streams is mapped to obtain the x second data streams, wherein n≥2.

30. The ethernet device according to claim 24 , wherein a granularity of the block-level demultiplexing processing is a quantity of bits comprised in one forward error correction (FEC) symbol.