Decision feedback equalization with efficient burst error correction
Receivers, methods, and cores, can provide decision feedback equalization with efficient burst error correction. An illustrative receiver includes: a decision feedback equalizer that derives symbol decisions from a receive signal; a subtractor that determines an equalization error for each said symbol decision; and a post-processor that operates on the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative receiving method includes: using a decision feedback equalizer to derive symbol decisions from a filtered receive signal; determining an equalization error for each said symbol decision; and processing the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative semiconductor intellectual property core generates circuitry for implementing a receiving and method as described above.
1. A receiver comprising:
a decision feedback equalizer that derives symbol decisions from a filtered receive signal;
a subtractor that determines an equalization error for each symbol decision; and
a post-processor that operates on the symbol decisions and the equalization errors to detect and correct symbol decision error bursts.
2. The receiver of claim 1 , wherein the post-processor detects burst error exit symbols by comparing a magnitude of the equalization errors to a threshold.
3. The receiver of claim 2 , further comprising a feed forward filter that operates on a receive signal to provide the filtered receive signal, thereby shaping a channel response to 1+γD, wherein D is a unit delay operator and γ is a coefficient representing trailing intersymbol interference.
4. The receiver of claim 3 , wherein the threshold is programmable.
5. The receiver of claim 2 , wherein the decision feedback equalizer derives M-ary PAM symbol decisions, M>2, and the burst error exit symbols are limited to 0 and (M−1).
6. The receiver of claim 2 , wherein the post-processor includes a metric circuit to determine a likelihood difference for each of multiple different error burst lengths.
7. The receiver of claim 6 , wherein the post-processor further includes a corrector circuit that finds a minimum likelihood difference and, if the minimum likelihood difference so indicates, corrects a corresponding number of decision errors preceding the burst error exit symbol.
8. The receiver of claim 7 , wherein the metric circuit and the corrector circuit are disabled until a burst error exit symbol is detected.
9. A receiving method comprising:
using a decision feedback equalizer to derive symbol decisions from a filtered receive signal;
determining an equalization error for each symbol decision; and
processing the symbol decisions and the equalization errors to detect and correct symbol decision error bursts.
10. The method of claim 9 , wherein said processing includes comparing the equalization errors to a threshold to detect burst error exit symbols.
11. The method of claim 10 , wherein a channel response of the filtered receive signal is 1+γD, wherein D is a unit delay operator and γ is a coefficient representing trailing intersymbol interference, and wherein the threshold equals γ.
12. The method of claim 10 , wherein the decision feedback equalizer derives M-ary PAM symbol decisions, M>2, and wherein as part of detecting the burst error exit symbols, said comparing is performed only for minimum and maximum symbol decision values.
13. The method of claim 10 , wherein said processing includes determining a likelihood difference for each of multiple different error burst lengths.
14. The method of claim 13 , wherein said processing further includes finding a minimum likelihood difference for each burst error exit symbol and, if the minimum likelihood difference is negative, corrects a corresponding number of decision errors preceding that burst error exit symbol.
15. A semiconductor intellectual property core that generates circuitry comprising:
a decision feedback equalizer that derives symbol decisions from a filtered receive signal;
a subtractor that determines an equalization error for each symbol decision; and
a post-processor that operates on the symbol decisions and the equalization errors to detect and correct symbol decision error bursts.
16. The semiconductor intellectual property core of claim 15 , wherein the post-processor comprises a comparator that compares the equalization errors to a threshold to detect burst error exit symbols.
17. The semiconductor intellectual property core of claim 16 , wherein a channel response of the filtered receive signal is 1+γD, wherein D is a unit delay operator and γ is a coefficient representing trailing intersymbol interference, and wherein the threshold is programmable.
18. The semiconductor intellectual property core of claim 16 , wherein the decision feedback equalizer derives M-ary PAM symbol decisions, M>2, and wherein said burst error exit symbols are limited to a minimum symbol decision value and a maximum symbol decision value.
19. The semiconductor intellectual property core of claim 16 , wherein the post-processor includes a metric circuit configured to determine a likelihood difference for each of multiple different error burst lengths.
20. The semiconductor intellectual property core of claim 19 , wherein the post-processor further includes a corrector circuit configured to find a minimum likelihood difference for each burst error exit symbol and, if the minimum likelihood difference indicates a decision error is present, configured to correct a corresponding number of decision errors preceding that burst error exit symbol.