Low dropout regulator and memory device including the same
Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.
1. A low dropout (LDO) regulator, comprising:
a first resistor;
a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node;
an operational amplifier including input terminals respectively connected with a reference voltage and the first node, and an output terminal;
a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node;
a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node; and
a current source connected between the second node and a ground voltage terminal.
2. The LDO regulator as claimed in claim 1 , further comprising:
a capacitor connected between the power supply voltage terminal and the second end of the first resistor.
3. The LDO regulator as claimed in claim 2 , wherein the first resistor and the capacitor constitute a low pass filter.
4. The LDO regulator as claimed in claim 2 , wherein the third transistor, the first resistor, and the capacitor constitute an active inductor.
5. The LDO regulator as claimed in claim 1 , wherein the third transistor, the first resistor, and a gate-source capacitance of the third transistor constitute an active inductor.
6. The LDO regulator as claimed in claim 1 , further comprising:
a bias transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the third node, and a drain terminal connected with the second node.
7. The LDO regulator as claimed in claim 1 , further comprising:
a second resistor connected between the first node and the source terminal of the second transistor.
8. The LDO regulator as claimed in claim 1 , further comprising:
a third resistor connected between the first node and a voltage division node; and
a fourth resistor connected between the voltage division node and the ground voltage terminal.
9. The LDO regulator as claimed in claim 1 , further comprising:
a fifth resistor connected between the third node and the second node.
10. The LDO regulator as claimed in claim 1 , further comprising:
a fourth transistor including a gate terminal connected with a bias voltage terminal, a source terminal connected with the drain terminal of the third transistor, and a drain terminal connected with the third node.
11. The LDO regulator as claimed in claim 1 , wherein each of the first to third transistors is a p-channel metal-oxide-semiconductor (PMOS) transistor.