Memory device and method
View Patent ↗An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time-to-digital convertor converts a time associated with the output voltage to a digital value.
1. An Input/Output (I/O) circuit for a memory device, wherein the I/O circuit comprises:
a charge integration circuit coupled to a bitline of the memory device, wherein the charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline;
a comparator coupled to the charge integration circuit, wherein the comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison; and
a time-to-digital converter coupled to the comparator, wherein the time-to-digital convertor converts a time associated with the output voltage to a digital value.
2. The I/O circuit of claim 1 , wherein the time-to-digital convertor comprises a first delay circuit, a second delay circuit, and output circuits connected to the first delay circuit and the second delay circuit.
3. The I/O circuit of claim 2 , wherein the first delay circuit comprises a first plurality of delay elements connected in series, each of the first plurality of delay elements configured to delay a signal by a first predetermined delay time.
4. The I/O circuit of claim 2 , wherein the second delay circuit comprises a second plurality of delay elements connected in series, each of the second plurality of delay elements configured to delay an output voltage signal by a second predetermined delay time.
5. The I/O circuit of claim 2 , wherein each of the output circuits is configured to sample a predetermined signal and an output voltage signal and provide the digital value based on the sampling.
6. The I/O circuit of claim 2 , wherein the output circuits comprise a plurality of flip-flops.
7. The I/O circuit of claim 2 , wherein the output circuits comprise a plurality of multiplexers.
8. A memory device comprising:
a memory array comprising a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a bit line of a plurality of bitlines;
a plurality of multiplexers, each of the plurality of multiplexers associated with a predetermined number of bitlines of the plurality of bitlines; and
a plurality of Input/Output (I/O) circuits, wherein each of the plurality of I/O circuits is associated with one of the plurality of multiplexers, wherein a multiplexer connects an I/O circuit associated with the multiplexer to a bitline of the predetermined number of bitlines, and wherein the I/O circuit senses multiply-accumulate value for the bitline in time domain.
9. The memory device of claim 8 , wherein the I/O circuit comprises:
a charge integration circuit coupled to the bitline, wherein the charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline;
a comparator coupled to the charge integration circuit, wherein the comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison; and
a time-to-digital converter coupled to the comparator, wherein the time-to-digital convertor converts a time associated with the output voltage to a digital value.
10. The memory device of claim 9 , wherein the charge integration circuit comprises a charge circuit connected to a sensing node, wherein the charge circuit charges the sensing node at a first rate, and wherein the sensing node provides the sensing voltage.
11. The memory device of claim 10 , wherein the charge integration circuit further comprises a feedback circuit connected to the sensing node, wherein the feedback circuit charges the sensing node at a second rate.
12. The memory device of claim 11 , wherein the second rate is greater than the first rate.
13. The memory device of claim 8 , further comprising a controller, wherein the controller is operative to initiate a Multiply-Accumulate (MAC) operation.
14. The memory device of claim 13 , wherein the controller selects one of the plurality of multiplexers for the MAC operation, and wherein the selected one of the plurality of multiplexers connects the bitline to the I/O circuit.
15. A method of Multiply-Accumulate (MAC) operation in a memory device, the method comprising:
connecting a charge integration circuit to a bitline of the memory device;
charging, by the charge integration circuit, a sensing node based on a decrease of a voltage on the bitline;
comparing, by a comparator coupled to the charge integration circuit, a sensing voltage of the sensing node with a reference voltage;
providing, by the comparator, an output voltage based on the comparison; and
converting, by a time-to-digital converter coupled to the comparator, a time associated with the output voltage to a MAC value.
16. The method of claim 15 , wherein charging the sensing node comprises charging the sensing node at a first rate till the sensing voltage is pulled to a threshold voltage.
17. The method of claim 16 , wherein charging the sensing node comprises charging the sensing node at a second rate after the sensing voltage is pulled to the threshold voltage.
18. The method of claim 17 , wherein the second rate is greater than the first rate.
19. The method of claim 15 , wherein charging the sensing node comprises:
charging the sensing node based on discharge rate of a bitline voltage of the bitline.
20. The method of claim 15 , wherein connecting the charge integration circuit to the bitline comprises connecting the charge integration circuit to the bitline through a multiplexer.