Memory device having multiple chips and method for manufacturing the same
According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.
1. A method for manufacturing a memory device, comprising:
forming an oxide layer on a first substrate by anodic oxidation, the oxide layer including a plurality of first holes arranged at first intervals and a plurality of second holes arranged at second intervals;
forming a plurality of memory units in the first holes, respectively and forming a plurality of first mark portions in the second holes, respectively;
forming a first insulating layer on the oxide layer, the first insulating layer including a first pad in a first surface of the first insulating layer; and
bonding the first surface of the first insulating layer, to a second surface of a second substrate on which a second pad is provided, a position of the first substrate and a position of the second substrate being aligned with each other based on the plurality of first mark portions and a second mark portion of the second substrate, the plurality of first mark portions and the second mark portion being electrically isolated from the plurality of memory units and a circuit of the second substrate.
2. The method of claim 1 , wherein
after forming a plurality of first members of the plurality of memory units in the plurality of first holes and the plurality of second holes, respectively,
the plurality of first mark portions are formed by forming a plurality of second members on the plurality of first members in the plurality of second holes, the plurality of second members being different from the plurality of first members, and each of the plurality of first mark portions including one of the plurality of first members and one of the plurality of second members.
3. The method of claim 1 , wherein the first substrate and the second substrate are aligned with each other using at least one of a third mark portion which is formed in the first insulating layer using the plurality of first mark portions or a fourth mark portion which is formed in a second insulating layer on the second substrate using the second mark portion of the second substrate.
4. The method of claim 1 , wherein lithography alignment is performed to form the first pad using the plurality of first mark portions.
5. The method of claim 1 , wherein lithography alignment is performed to form the first pad using a third mark portion which is formed in the first insulating layer using the plurality of first mark portions.
6. The method of claim 1 , further comprising removing the first substrate after the first surface is bonded to the second surface.
7. The method of claim 1 , wherein
each of the plurality of memory units includes a first magnetic body, and
each of the plurality of first mark portions includes a second magnetic body.
8. The method of claim 1 , wherein
each of the plurality of memory units includes a capacitor including a first conductive portion, a second conductive portion, and a first insulating portion between the first conductive portion and the second conductive portion, and
each of the plurality of first mark portions includes a third conductive portion, a fourth conductive portion, and a second insulating portion between the third conductive portion and the fourth conductive portion.
9. The method of claim 1 , wherein the plurality of first mark portions are formed in a flat region of the oxide layer, the flat region being in contact with the first insulating layer.