Module and methods of assembly for large area flat panel detectors
An image sensor unit is disclosed that includes an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable. Each row of pixels is controlled via a row control in communication with the row of pixels in the array via a row addressing line, and capable of selectively addressing one or more of the plurality of rows. Each column of pixels is controlled by a column control in communication with each column of pixels in the array via a column addressing line, and capable of selectively addressing one or more of the plurality of columns. A unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row and column control to address one or more specific rows and columns of the array. A flat panel image sensor may include image sensor chips mounted on a substrate, the substrate may include a plurality of openings, and each of the plurality of openings enables access to at least one image sensor unit of the image sensor units. Each image sensor chip may include at least one chip contact array where at least one contact of each image sensor unit is accessible through at least one opening. The flat panel image sensor also may include a printed circuit board (“PCB”) attached to the substrate, which includes PCB contact arrays and each PCB contact array may be in alignment with and in electrical connection with a corresponding chip contact array using electrically adhesive paste. The substrate and the PCB may be aligned so that each ball of electrically conductive adhesive paste is in contact with one electrical contact pad to form an image sensor assembly.
1. A method of constructing a flat panel image sensor, the method comprising:
mounting a plurality of image sensor chips on a substrate, wherein the substrate includes a plurality of openings, wherein each of the plurality of openings enables access to at least one image sensor unit of the plurality of image sensor units, and wherein each image sensor chip includes at least one chip contact array and wherein at least one contact of each image sensor unit is accessible through at least one opening, wherein the openings are through-holes that each correspond to a single contact of the plurality of image sensor units, optionally wherein the openings are electrically conductive through vias;
attaching a printed circuit board (“PCB”) to the substrate, wherein the PCB includes a plurality of PCB contact arrays, wherein each PCB contact array is configured to be placed in alignment and in electrical connection with a corresponding chip contact array;
forming on each PCB contact array and each chip contact array a ball of electrically conductive adhesive paste;
aligning the substrate and the PCB so that each ball of electrically conductive adhesive paste is in contact with one electrical contact pad to form an image sensor assembly; and
curing the image sensor assembly.
2. The method according to claim 1 , further comprising injecting underfill into at least one of the through-holes to provide additional structural support for the large area flat panel image sensor.
3. The method according to claim 1 , wherein each of the plurality of image sensor units comprises:
a memory configured to store pixel locations, wherein the pixel locations specify one or more of a pre-defined readout pattern of pixels, pixels marked for repair, and pixels marked to skip readout; and
at least one signal amplifier configured to output amplified signals.
4. The method according to claim 1 , further comprising mounting the image sensor chips onto substrate first at a center of the substrate, then progressively outward toward one or more edges of the substrate.
5. The method according to claim 1 , wherein the substrate includes an opening for every at least two image sensor units.
6. The method according to claim 1 , wherein the PCB is attached to the substrate using conventional soldering, or anisotropic conductive film or the like.
7. The method according to claim 1 , wherein the openings are electrically conductive through vias.