Channel structures for semiconductor devices
View Patent ↗The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.
1. A method, comprising:
forming a superlattice structure comprising a plurality of first nanostructured layers and a plurality of second nanostructured layers on a substrate;
removing the plurality of second nanostructured layers to form a plurality of gate openings;
forming a germanium epitaxial layer on the plurality of first nanostructured layers at a first temperature;
performing a temperature ramping process for a first period of time to increase the first temperature to a second temperature; and
annealing the germanium epitaxial layer at the second temperature for a second period of time to form a cladding layer surrounding the plurality of first nanostructured layers.
2. The method of claim 1 , wherein the first period of time is greater than the second period of time.
3. The method of claim 1 , wherein forming the germanium epitaxial layer comprises performing a chemical vapor deposition (CVD) process with a precursor process gas of germane (GeH 4 ), digermane (Ge 2 H 6 ), higher order germane (Ge> 2 H> 6 ), or a combination thereof.
4. The method of claim 1 , wherein forming the germanium epitaxial layer comprises using a physical vapor deposition (PVD) process, a molecular beam epitaxy (MBE) process, or an atomic layer deposition (ALD) process.
5. The method of claim 1 , wherein forming the germanium epitaxial layer comprises forming the germanium epitaxial layer with one or more three-dimensional germanium islands.
6. The method of claim 5 , wherein annealing the germanium epitaxial layer comprises removing the one or more three-dimensional germanium islands from surfaces of the cladding layer.
7. The method of claim 1 , wherein annealing the germanium epitaxial layer comprises performing an in-situ annealing process on the germanium epitaxial layer to diffuse germanium atoms of the germanium epitaxial layer into the plurality of first nanostructured layers and form the cladding layer comprising a germanium-silicon alloy layer.
8. The method of claim 1 , wherein annealing the germanium epitaxial layer comprises performing the annealing at an annealing temperature between about 450° C. and about 1200° C.
9. A method, comprising:
performing an epitaxial process at a first temperature on nanostructured layers on a substrate to form a germanium epitaxial layer on the nanostructured layers;
performing a temperature ramping process for a first period of time to increase the first temperature to a second temperature;
performing an annealing process on the germanium epitaxial layer at the second temperature for a second period of time to form a cladding layer with a first thickness surrounding the nanostructured layers; and
forming a gate structure on the cladding layer.
10. The method of claim 9 , wherein the first period of time is greater than the second period of time.
11. The method of claim 9 , wherein performing the epitaxial process comprises performing a chemical vapor deposition (CVD) process with a precursor process gas of germane (GeH 4 ), digermane (Ge 2 H 6 ), higher order germane (Ge>2H>6), or a combination thereof.
12. The method of claim 9 , wherein performing the epitaxial process comprises using a physical vapor deposition (PVD) process, a molecular beam epitaxy (MBE) process, or an atomic layer deposition (ALD) process.
13. The method of claim 9 , further comprising repeating the epitaxial process, the temperature ramping process, and the annealing process on the cladding layer to increase the first thickness of the cladding layer to a second thickness.
14. The method of claim 9 , wherein performing the annealing process on the germanium epitaxial layer comprises performing the annealing process at an annealing temperature between about 450° C. and about 1200° C. for an annealing time between about 1 microsecond and about 3600 seconds.
15. The method of claim 9 , wherein performing the annealing process on the germanium epitaxial layer comprises performing an in-situ annealing process.
16. A method, comprising:
forming nanostructured layers on a substrate;
forming a source/drain (S/D) region adjacent to the nanostructured layers;
forming a silicon-germanium alloy layer surrounding the nanostructured layers, wherein forming the silicon-germanium alloy layer comprises:
epitaxially growing a germanium layer on the nanostructured layers, and
performing an annealing process on the germanium layer; and
forming a gate structure on the silicon-germanium alloy layer.
17. The method of claim 16 , wherein epitaxially growing the germanium layer comprises epitaxially growing the germanium layer with three-dimension islands on a top surface of the germanium layer.
18. The method of claim 16 , wherein performing the annealing process comprises performing an in-situ annealing process.
19. The method of claim 16 , further comprising epitaxially growing another germanium layer on the silicon-germanium alloy layer.
20. The method of claim 19 , further comprising performing another annealing process on the other germanium layer.