Radio frequency switching time reducing circuit
A switching circuit comprises a radio frequency (RF) switch, a gate resistor, a voltage source, a transmission gate, and coupling circuitry configured to couple a gate of the RF switch, a first side of the gate resistor, and the transmission gate at a first node and the voltage source, a second side of the gate resistor, and the transmission gate at a second node.
1. A switching circuit comprising:
a radio frequency (RF) switch including a gate;
a gate resistor coupled at a first side of the gate resistor to the gate the RF switch at a first node;
a voltage source coupled to a second side of the gate resistor at a second node;
a transmission gate including a first semiconductor and a second semiconductor, the transmission gate being coupled to the first side of the gate resistor and the gate of the RF switch at the first node and further being coupled to the voltage source and the second side of the gate resistor at the second node;
a first level shifter coupled to the first semiconductor and configured to supply voltage pulses to the first semiconductor; and
a second level shifter coupled to the second semiconductor and configured to supply voltage pulses to the second semiconductor.
2. The switching circuit of claim 1 wherein the first semiconductor comprises a p-channel metal-oxide-semiconductor (PMOS).
3. The switching circuit of claim 2 wherein the second semiconductor comprises an n-channel metal-oxide-semiconductor (NMOS).
4. The switching circuit of claim 3 wherein a source of the PMOS is coupled to a drain of the NMOS.
5. The switching circuit of claim 3 wherein a drain of the PMOS is coupled to a source of the NMOS.
6. The switching circuit of claim 3 wherein the gate of the RF switch, the first side of the gate resistor, a drain of the PMOS, and a source of the NMOS are coupled at the first node.
7. The switching circuit of claim 3 wherein the voltage source, the second side of the gate resistor, a source of the PMOS, and a drain of the NMOS are coupled at the second node.
8. The switching circuit of claim 1 wherein the first level shifter and the second level shifter are configured to apply complementary dynamic pulses to the first semiconductor and the second semiconductor.
9. The switching circuit of claim 8 wherein the transmission gate is configured to short out the gate resistor.
10. The switching circuit of claim 1 wherein the first level shifter and the second level shifter are configured to turn on when the RF switch is turned on.
11. The switching circuit of claim 1 further comprising a first voltage pulse source coupled to the first level shifter.
12. The switching circuit of claim 11 further comprising a second voltage pulse source coupled to the second level shifter.
13. The switching circuit of claim 1 wherein the gate resistor is coupled in parallel with the transmission gate.
14. A circuit comprising:
a radio frequency (RF) switch including a gate;
a transmission gate including a p-channel metal-oxide-semiconductor (PMOS) and an n-channel metal-oxide-semiconductor (NMOS), the transmission gate being coupled to the gate of the RF switch and being configured to provide dynamic complementary pulsing voltages to the RF switch;
a first level shifter coupled to the PMOS and configured to supply voltage pulses to the PMOS; and
a second level shifter coupled to the NMOS and configured to supply voltage pulses to the NMOS.
15. The circuit of claim 14 further comprising a gate resistor, wherein the gate of the RF switch, the gate resistor, and the transmission gate are coupled at a first node.
16. The circuit of claim 15 wherein the transmission gate is configured to short out the gate resistor in response to the RF switch turning on.