Energy-efficient SFQ logic biasing technique
Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being connected to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor. A source of an electrical current source that is external to the first cell is connected to the first shunted junction and the first resistor at a common point.
1. An electronic structure, comprising:
a first cell comprising:
a first shunted Josephson junction;
a first inductor connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor being connected to a feed point of the first cell; and
a first resistor having a first end connected to ground and a second end connected to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor.
2. The electronic structure of claim 1 , further comprising:
a source of an electrical current that is external to the first cell, wherein the source of the electrical current is connected to the first shunted Josephson junction and the first resistor at a common point.
3. The electronic structure of claim 1 , wherein an electrical current to the feed point of the first cell when powered varies by less than 10 percent.
4. The electronic structure of claim 1 , wherein the first inductor is adapted to filter alternating current (AC) component of an electrical current flowing through the first inductor to the feed point of the first cell.
5. The electronic structure of claim 2 , further comprising:
a second cell comprising
a second shunted Josephson junction;
a second inductor connected in series with the second shunted Josephson junction at a first terminal end of the second inductor and a second terminal end of the second inductor being connected to a feed point of the second cell; and
a second resistor having a first end connected to the ground and a second end connected to the second shunted Josephson junction at a terminal of second shunted Josephson junction that is not connected to the second inductor and at which the source of the electrical current is applied.
6. The electronic structure of claim 5 , wherein the first inductor or the second inductor is a narrow or twisted strip.
7. The electronic structure of claim 5 , wherein the first cell or the second cell is a parametrized cell.
8. The electronic structure of claim 5 , wherein the electronic structure is implemented as one or more geometrical mask features on a mask set or an integrated circuit.
9. A method of designing an electronic structure, the method comprising:
connecting a first inductor in series with a first shunted Josephson junction at a first terminal end of the first inductor;
connecting a second terminal end of the first inductor to a feed point of a first cell comprising the first inductor, the first shunted Josephson junction, and a first resistor;
connecting a first end of the first resistor to ground and a second end of the first resistor to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor; and
powering the first cell using an electrical current source, wherein the electrical current source is external to the first cell, and wherein the electrical current source is connected to the first shunted Josephson junction and the first resistor at a common point.
10. The method of claim 9 , wherein an electrical current to the feed point of the first cell being powered varies by less than 10 percent.
11. The method of claim 9 , wherein the first inductor is adapted to filter alternating current (AC) components of an electrical current flowing through the first inductor to the feed point of the first cell.
12. The method of claim 9 , further comprising:
connecting a second inductor in series with a second shunted Josephson junction at a first terminal end of the second inductor;
connecting a second terminal end of the second inductor to a feed point of a second cell; and
connecting a first end of a second resistor to the ground and a second end of the second resistor to the second shunted Josephson junction at a terminal of the second shunted Josephson junction that is not connected to the second inductor and at which the electrical current source is applied.
13. The method of claim 12 , further comprising:
forming the first inductor or the second inductor in a twisted strip.
14. The method of claim 12 , further comprising:
designing the first cell or the second cell as a parametrized cell.