Methods and apparatus to write data to registers

1. An apparatus to write data to registers comprising:

interface circuitry to receive an analog signal; and

sequencer circuitry to:

determine whether the apparatus is to operate in a single transfer state or a multiple transfer state;

access a configuration from a control register in a plurality of control registers;

initiate a conversion of the analog signal to a digital value based on the configuration; and

write the digital value to a result register in a plurality of result registers based on the determination.

2. The apparatus of claim 1 , wherein the sequencer circuitry is further to:

determine which control register to access the configuration from based on a read pointer; and

determine which result register to write the digital value to based on a write pointer.

3. The apparatus of claim 2 , wherein:

the conversion is a first conversion;

the configuration is a first configuration;

the control register is a first control register; and

the sequencer circuitry is to further:

determine whether a second conversion should produce a digital value based on the first configuration or a second configuration; and

in response to a determination that the second conversion should produce a digital value based on the second configuration, update the read pointer to identify a second control register in the plurality of control registers.

4. The apparatus of claim 2 , wherein the sequencer circuitry is further to, in response to a determination that the apparatus is to operate in the multiple transfer state, update the write pointer to identify a result register with an index that matches a control register identified by the read pointer.

5. The apparatus of claim 2 , wherein the plurality of result registers is ordered from a first result register to a last result register, and wherein, in response to a determination that apparatus is to operate in the single transfer state, the sequencer circuitry is further to:

initially set the write pointer to identify the first result register;

determine, based on the order and a current result register identified by the write pointer, a next result register that the digital value should be written to; and

update the write pointer to identify the next result register.

6. The apparatus of claim 5 , wherein:

the sequencer circuitry is to determine the next result register to be the first result register when the current result register identified by the write pointer is the last result register; and

the sequencer circuitry is to determine the next result register regardless of whether the next result register has an index that matches a control register identified by the read pointer.

7. The apparatus of claim 1 , further including:

Direct Memory Access (DMA) circuitry to transfer one or more digital values from the plurality of result registers to main memory; and

a software application to access the one or more digital values in main memory.

8. The apparatus of claim 7 , wherein:

the digital value is a first digital value;

in response to a determination that the apparatus is to operate in the multiple transfer state, the DMA circuitry is to transfer the first digital value to main memory in a first transfer;

the sequencer circuitry is to further write a second digital value to a result register in the plurality of result registers; and

in response to a determination that the apparatus is to operate in the multiple transfer state, the DMA circuitry is to transfer the second digital value to main memory in a second transfer.

9. The apparatus of claim 7 , wherein:

the digital value is a first digital value;

in response to a determination that the apparatus is to operate in a single transfer state:

the sequencer circuitry is to further determine whether a number of digital values stored in the plurality of result registers satisfies a threshold; and

in response to a determination that the number of digital values stored in the plurality of result registers satisfies the threshold, the DMA circuitry is to transfer the number of digital values to main memory in a single transfer.

10. The apparatus of claim 7 , further including virtual address mapper circuitry to, in response to a determination that the apparatus is to operate in the single transfer state, map the plurality of result registers to a single virtual address to support DMA circuitry that does not implement wrap around addressing.

11. The apparatus of claim 7 , wherein:

the sequencer circuitry is to determine whether the apparatus is to operate in the single transfer state or the multiple transfer state based on the software application;

the software application is a first software application;

the apparatus is to operate in the single transfer state for a first amount of time based on the first software application; and

the apparatus is to operate in the multiple transfer state for a second amount of time based on a second software application.

12. At least one non-transitory machine-readable medium comprising instructions that, when executed, cause at least one processor to at least:

receive an analog signal;

determine whether to operate in a single transfer state or a multiple transfer state;

access a configuration from a control register in a plurality of control registers;

initiate a conversion of the analog signal to a digital value based on the configuration; and

write the digital value to a result register in a plurality of result registers based on the determination.

13. The at least one non-transitory machine-readable medium of claim 12 , wherein the instructions, when executed, cause the at least one processor to:

determine which control register to access the configuration from based on a read pointer; and

determine which result register to write the digital value to based on a write pointer.

14. The at least one non-transitory machine-readable medium of claim 13 , wherein:

the conversion is a first conversion;

the configuration is a first configuration;

the control register is a first control register; and

the instructions, when executed, cause the at least one processor to:

determine whether a second conversion should produce a digital value based on the first configuration or a second configuration; and

in response to a determination that the second conversion should produce a digital value based on the second configuration, update the read pointer to identify a second control register in the plurality of control registers.

15. The at least one non-transitory machine-readable medium of claim 13 , wherein the instructions, when executed, cause the at least one processor to:

in response to a determination to operate in the multiple transfer state, update the write pointer to identify a result register with an index that matches a control register identified by the read pointer.

16. The at least one non-transitory machine-readable medium of claim 13 , wherein the plurality of result registers is ordered from a first result register to a last result register, and wherein, in response to a determination to operate in the single transfer state, the instructions, when executed, cause the at least one processor to:

initially set the write pointer to identify the first result register;

determine, based on the order and a current result register identified by the write pointer, a next result register that the digital value should be written to; and

update the write pointer to identify the next result register.

17. The at least one non-transitory machine-readable medium of claim 16 , wherein the instructions, when executed, cause the at least one processor to:

determine the next result register to be the first result register when the current result register identified by the write pointer is the last result register; and

determine the next result register regardless of whether the next result register has an index that matches a control register identified by the read pointer.

18. The at least one non-transitory machine-readable medium of claim 12 , wherein the instructions, when executed, cause the at least one processor to:

operate in the single transfer state for a first amount of time based on the a software application; and

operate in the multiple transfer state for a second amount of time based on a second software application.

19. A method to write data to registers comprising:

receiving an analog signal;

determining whether to operate in a single transfer state or a multiple transfer state;

accessing a configuration from a control register in a plurality of control registers;

initiating a conversion of the analog signal to a digital value based on the configuration; and

writing the digital value to a result register in a plurality of result registers based on the determination.

20. The method of claim 19 , further including:

operating in the single transfer state for a first amount of time based on a first software application; and

operating in the multiple transfer state for a second amount of time based on a second software application.