IP Library › Granted Patent US 11,948,976
Granted Patent B2
US 11,948,976 · App. 17/514,673 · Granted Apr 2, 2024

Vertical MOSFET having trench gate structure containing silicon carbide

Inventors: Takeshi Tawara (Tsukuba, JP); Hidekazu Tsuchida (Yokosuka, JP); Koichi Murata (Yokosuka, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/0878H01L29/167H01L29/7805H01L29/1608H01L29/7813
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Quick Facts
Patent No.
US 11,948,976
App. No.
17/514,673
Granted
Apr 2, 2024
Kind
B2
Abstract

A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films. A lifetime of the minority carrier of the first semiconductor region is shorter than that of the rest of the second first-conductivity-type epitaxial layer.

Claims (28)

1. A vertical metal oxide semiconductor field effect transistor (MOSFET) containing silicon carbide and having a pn junction interface through which a current passes in a forward direction, the vertical MOSFET comprising:

a starting substrate of a first conductivity type, having a first surface and a second surface opposite to each other;

a first first-conductivity-type epitaxial layer containing silicon carbide;

a second first-conductivity-type epitaxial layer containing silicon carbide, provided on the first surface of the starting substrate via the first first-conductivity-type epitaxial layer, the second first-conductivity-type epitaxial layer containing silicon carbide having an impurity concentration lower than an impurity concentration of the starting substrate and an impurity concentration of the first first-conductivity-type epitaxial layer, the second first-conductivity-type epitaxial layer further containing, as an impurity thereof, a first element that is a dopant of the first conductivity type;

a first semiconductor region of the first conductivity type, provided as a portion of the second first-conductivity-type epitaxial layer, in contact with the first first-conductivity-type epitaxial layer, the first semiconductor region having, as an impurity thereof, the first element and a second element, the second element forming recombination centers;

a second-conductivity-type epitaxial layer containing silicon carbide, the second-conductivity-type epitaxial layer forming the pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer that includes the first semiconductor region;

a plurality of second semiconductor regions of the first conductivity type, selectively provided in the second-conductivity-type epitaxial layer;

a plurality of trenches that penetrate through the plurality of second semiconductor regions, respectively, and through the second-conductivity-type epitaxial layer, and reach the second first-conductivity-type epitaxial layer;

a plurality of gate electrodes that are provided in the plurality of trenches via a plurality of gate insulating films, respectively;

a first electrode electrically connected to the second semiconductor regions and the second-conductivity-type epitaxial layer; and

a second electrode electrically connected to the second surface of the starting substrate, wherein

a lifetime of the minority carrier of the first semiconductor region is shorter than a lifetime of the minority carrier of another portion of the second first-conductivity-type epitaxial layer excluding the first semiconductor region,

a concentration of the second element in the first semiconductor region is at most 1/10 of a concentration of the first element in the second first-conductivity-type epitaxial layer,

the first element is nitrogen,

the second element is vanadium, and

the concentration of the second element in the first semiconductor region is in a range from 5×10 13 /cm 3 to 1×10 15 /cm 3 .

2. The vertical MOSFET according to claim 1 , wherein

the concentration of the second element is at least 1×10 14 /cm 3 .

3. The vertical MOSFET according to claim 1 , wherein

the concentration of the first element in the first semiconductor region is in a range from 8.0×10 15 /cm 3 to 1.0×10 16 /cm 3 .

4. The vertical MOSFET according to claim 1 , wherein

the first first-conductivity-type epitaxial layer has a thickness in a range from 3 μm to 6.5 μm, and the impurity concentration thereof is in a range from 7.0×10 18 /cm 3 to 2.0×10 19 /cm 3 .

5. The vertical MOSFET according to claim 1 , wherein

the first semiconductor region has a thickness that is in a range from 1 μm to 5 μm.

6. The vertical MOSFET according to claim 1 , wherein

the lifetime of the minority carrier of the first semiconductor region is in a range from 0.01 μs to 0.1 μs.

7. The vertical MOSFET according to claim 1 , wherein

a breakdown voltage of the vertical MOSFET is 1.2 kV.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2021
From: TAWARA, TAKESHI; TSUCHIDA, HIDEKAZU; MURATA, KOICHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 057964/0770 →
Priority Claims (1)
JP 2020-207277 · Dec 15, 2020 · national
Continuity (1)
Related Publication 20220190114A1 · Jun 16, 2022