Semiconductor device and method

1. A method comprising:

forming a dummy gate on a channel region of a semiconductor fin, the semiconductor fin protruding above an isolation region;

growing a source/drain region in the semiconductor fin adjacent the dummy gate;

depositing an etch stop layer on the source/drain region;

forming an inter-layer dielectric on the etch stop layer;

removing the dummy gate to expose the channel region of the semiconductor fin;

after removing the dummy gate, trimming the channel region by performing a plurality of oxidation and etch cycles, each of the oxidation and etch cycles removing a same amount of the channel region;

after trimming the channel region, forming a metal gate on the channel region, the metal gate extending along a sidewall of the channel region and along a top surface of the isolation region; and

forming a source/drain contact through the inter-layer dielectric and the etch stop layer, the source/drain contact coupled to the source/drain region, wherein the inter-layer dielectric and the etch stop layer are each between the source/drain contact and the metal gate.

2. The method of claim 1 further comprising:

forming a gate contact coupled to the metal gate, a height of the source/drain contact being greater than a height of the gate contact.

3. The method of claim 1 , wherein trimming the channel region reduces a width of the channel region by 0.5% to 50%.

4. The method of claim 1 , wherein trimming the channel region reduces a height of the channel region by 0.5% to 15%.

5. The method of claim 1 , wherein each oxidation cycle comprises a thermal oxidation process performed at a temperature of from 300° C. to 1050° C. and for a time span of from 10 seconds to 600 seconds.

6. The method of claim 1 , wherein each etch cycle comprises a chemical oxide removal performed with dilute hydrofluoric acid.

7. A method comprising:

forming a semiconductor fin protruding above an isolation region;

forming a dummy gate on a channel region of the semiconductor fin, the channel region having a height above the isolation region, the channel region having a width;

removing the dummy gate from the channel region;

after removing the dummy gate, trimming the channel region to reduce the height and the width of the channel region; and

after trimming the channel region, forming a metal gate on the channel region.

8. The method of claim 7 , wherein the trimming the channel region comprises:

oxidizing surfaces of the channel region; and

removing the oxidized surfaces of the channel region,

wherein the oxidizing and the removing are cyclically repeated a predetermined quantity of times.

9. The method of claim 8 , wherein the oxidizing the surfaces of the channel region comprises:

performing a thermal oxidation process on the channel region, the thermal oxidation process being performed at a temperature of from 300° C. to 1050° C., and for a time span of from 10 seconds to 600 seconds.

10. The method of claim 8 , wherein oxidizing the surfaces of the channel region comprises:

exposing the channel region to a chemical oxidizer.

11. The method of claim 8 , wherein the removing the channel region comprises:

etching the oxidized surfaces of the channel region with dilute hydrofluoric acid.

12. The method of claim 7 , wherein the trimming the channel region comprises:

etching surfaces of the channel region for a predetermined amount of time.

13. The method of claim 12 , wherein the etching the surfaces of the channel region comprises:

performing a wet etch on the channel region with etchants comprising diluted hydrofluoric acid, a buffered oxide etchant, standard clean-1, standard clean-2, or a sulfuric acid-hydrogen peroxide mixture for a time span of from 3 seconds to 100 seconds.

14. The method of claim 12 , wherein the etching the surfaces of the channel region comprises:

performing a dry etch on the channel region with etchants comprising a fluorocarbon gas, a chlorofluorocarbon gas, a carbon chloride gas, hydrogen fluoride gas, hydrogen chloride gas, or hydrogen bromide gas for a time span of from 3 seconds to 100 seconds.

15. The method of claim 7 further comprising:

before removing the dummy gate, growing a source/drain region in the semiconductor fin adjacent the dummy gate;

forming an inter-layer dielectric on the source/drain region; and

forming a source/drain contact through the inter-layer dielectric, the source/drain contact coupled to the source/drain region.

16. A method comprising:

removing a dummy gate from a semiconductor fin to expose a channel region of the semiconductor fin, the channel region adjacent a lightly doped source/drain region of the semiconductor fin;

after removing the dummy gate, oxidizing a portion of the channel region;

removing the oxidized portion of the channel region, a first width of the lightly doped source/drain region being greater than a second width of the channel region, a first height of the lightly doped source/drain region being greater than a second height of the channel region; and

forming a metal gate on the channel region.

17. The method of claim 16 , wherein a transition from the first width of the lightly doped source/drain region to the second width of the channel region has a step interface shape.

18. The method of claim 16 , wherein a transition from the first width of the lightly doped source/drain region to the second width of the channel region has a linear interface shape.

19. The method of claim 16 , wherein a transition from the first width of the lightly doped source/drain region to the second width of the channel region has a curved interface shape.

20. The method of claim 16 , further comprising:

before removing the dummy gate, growing a source/drain region in the semiconductor fin, the source/drain region adjacent the lightly doped source/drain region.