High voltage polysilicon gate in high-K metal gate device

1. An integrated circuit (IC) comprising:

a semiconductor substrate comprising a first area and a second area;

a polysilicon gate formed in the first area, wherein the polysilicon gate comprises a polysilicon electrode and a gate dielectric layer between the polysilicon electrode and the semiconductor substrate;

a high-κ metal gate formed in the second area, wherein the high-κ metal gate comprises a metal electrode and a high-κ dielectric layer between the metal electrode and the semiconductor substrate; and

wherein the polysilicon electrode has a width that is greater than a width of the metal electrode;

the polysilicon gate is a high voltage gate having a threshold voltage higher than the high-κ metal gate;

the gate dielectric layer is thicker than the high-κ dielectric layer; and

upper surfaces of the polysilicon electrode and the metal electrode are coplanar.

2. An IC according to claim 1 , further comprising embedded flash memory.

3. An IC according to claim 1 , further comprising split gate flash memory disposed on the semiconductor substrate, wherein the high-κ metal gate is a logic device.

4. An IC according to claim 1 , wherein the polysilicon gate has an area greater than one μm 2 .

5. An IC according to claim 1 , wherein a threshold voltage of the high-κ metal gate would be altered by a 5 second heat treatment at 1000° C.

6. An IC according to claim 1 , wherein the polysilicon gate has a gate dielectric layer adapted for operation with a gate voltage of 10V or higher.

7. An integrated circuit (IC) comprising:

a semiconductor substrate;

a plurality of metal gates disposed on the semiconductor substrate, wherein the metal gates comprise metal electrodes and high-κ dielectrics; and

a plurality of polysilicon gates disposed on the semiconductor substrate, wherein the polysilicon gates comprise polysilicon electrodes and gate dielectrics;

wherein the gate dielectrics have lower dielectric constants that the high-κ dielectrics;

the polysilicon electrodes have larger areas area than the metal electrodes;

the polysilicon electrodes have top surfaces that are coplanar with top surfaces of the metal electrodes; and

one or more of the plurality of polysilicon gates is a high voltage transistor having a threshold voltage of at least 10V.

8. An IC according to claim 7 , further comprising split gate flash memory disposed on the semiconductor substrate.

9. An IC according to claim 7 , wherein the plurality of polysilicon gates have areas greater than a design limit for the plurality of metal gates.

10. An IC according to claim 7 , wherein:

the semiconductor substrate is implanted with dopants in source and drain regions of the plurality of metal gates;

the source and drain regions have physical structures resulting from annealing after the dopants were implanted; and

the plurality of metal gates have structures that would not be possible if the plurality of metal gates had been subjected to the annealing.

11. An IC according to claim 7 , wherein:

the plurality of polysilicon gates comprise channel regions, and the gate dielectrics span gaps between the channel regions and the polysilicon electrodes; and

the gate dielectrics have dielectric constants lower than the high-κ dielectrics.

12. An IC according to claim 7 , wherein the plurality of polysilicon gates have areas greater than one μm 2 .

13. A method of forming an integrated circuit (IC) comprising:

providing a semiconductor substrate comprising a first region and a second region;

forming a gate oxide layer in the first region;

forming a polysilicon layer over the first region and the second region, whereby the polysilicon layer forms over the gate oxide layer;

forming a protective layer over the polysilicon layer;

masking the first region;

with the protective layer masked in the first region, selectively removing the protective layer and the polysilicon layer from the second region;

forming a high-κ dielectric layer over the first region and the second region, wherein the protective layer separates the high-κ dielectric layer from the polysilicon layer in the first region;

forming a dummy electrode layer over the high-κ dielectric layer;

patterning the dummy electrode layer and the high-κ dielectric layer to form dummy gates having dummy electrodes in the second region while removing the dummy electrode layer and the high-κ dielectric layer from the first region;

after forming the dummy gates, patterning the protective layer and the polysilicon layer to define polysilicon gates having polysilicon electrodes in the first region;

forming spacers adjacent the dummy gates;

filling an area adjacent the spacers;

planarizing the first and second regions, wherein planarizing exposes the dummy electrodes and the polysilicon electrodes;

removing the dummy electrodes to form voided areas;

depositing metal over the first and second regions, whereby the metal fills the voided areas to form metal electrodes; and

planarizing the first and second regions to remove excess metal.

14. A method according to claim 13 , further comprising forming a hard mask over the dummy electrode layer before patterning the dummy electrode layer and the high-κ dielectric layer to form dummy gates.

15. A method according to claim 13 , further comprising performing a silicide process on the polysilicon gates after planarizing the first and second regions to remove excess metal.

16. A method according to claim 13 , wherein the polysilicon gates each have an area greater than one μm 2 .

17. A method according to claim 13 , wherein the polysilicon gates are operative as high voltage gates.

18. A method according to claim 13 , wherein the gate oxide layer has a thickness adapted for a gate voltage of 10V or higher.

19. A method according to claim 13 , further comprising forming flash memory devices in a third region of the semiconductor substrate.

20. A method according to claim 13 , wherein the second region is masked while forming the gate oxide layer in the first region.