IP Library › Granted Patent US 11,953,629
Granted Patent B2
US 11,953,629 · App. 17/367,443 · Granted Apr 9, 2024

Light sensor and ranging method

Inventors: Ping-Hung Yin (Taipei, TW); Jia-Shyang Wang (Miaoli County, TW)
Assignee: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
G01S7/4865G01J1/44G01S7/4814G01S7/4816G01S7/484G01S7/4863G01S17/10G01S17/14G04F10/005H01L27/1446H01L27/14609H01L31/107G01J2001/442G01J2001/444G01J2001/4466G01J2001/448
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Quick Facts
Patent No.
US 11,953,629
App. No.
17/367,443
Granted
Apr 9, 2024
Kind
B2
Abstract

A light sensor and a ranging method are provided. The light sensor includes a light source, a sensing sub-pixel, and a control circuit. The sensing sub-pixel includes a diode. The control circuit operates the diode in a Geiger mode or an avalanche linear mode. The control circuit includes a time-to-digital converter, and the time-to-digital converter includes a counting circuit. The counting circuit includes a plurality of counting units. When the time-to-digital converter receives a sensing signal provided by the sensing sub-pixel, the control circuit generates a plurality of count values according to the sensing signal through the counting units of the counting circuit, where the count values are histogram data corresponding to a distance sensing result.

Claims (48)

1. A light sensor, comprising:

a light source;

a sensing sub-pixel, comprising a diode; and

a control circuit, coupled to the light source and the sensing sub-pixel, and configured to operate the diode in a Geiger mode or an avalanche linear mode,

wherein the control circuit comprises a time-to-digital converter coupled to the sensing sub-pixel, and the time-to-digital converter comprises:

a counting circuit, coupled to the sensing sub-pixel, and comprising a plurality of counting units,

wherein when the time-to-digital converter receives a sensing signal provided by the sensing sub-pixel, the time-to-digital converter generates a plurality of counting values according to the sensing signal through the counting units of the counting circuit, wherein the counting values are histogram data corresponding to a distance sensing result.

2. The light sensor as claimed in claim 1 , wherein the time-to-digital converter further comprises a controller, a first switch, and a plurality of second switches,

wherein a first terminal of the first switch is coupled to the sensing sub-pixel, a second terminal of the first switch is coupled to a first terminal of the second switches, and a second terminal of the second switches is coupled to the counting units,

wherein the counting circuit outputs a first switching signal to the first switch, and the controller outputs a plurality of second switching signals to control the second switches,

wherein when the sensing sub-pixel provides the sensing signal, the first switch is turned on and at least one of the second switches is turned on, so that the sensing signal is written into one of the counting units,

wherein the sensing signal is a single photon sensing signal.

3. The light sensor as claimed in claim 2 , wherein the second switches are coupled to form a tree structure.

4. The light sensor as claimed in claim 2 , wherein a plurality of signal transmission paths respectively between the counting units and the first switch are sequentially closed in different periods.

5. The light sensor as claimed in claim 2 , wherein the counting units are respectively an up counter.

6. The light sensor as claimed in claim 2 , wherein the counting units output the counting values of a counting result of a plurality of single photon sensing signals of the sensing signal during a sensing period, so that the time-to-digital converter generates the histogram data corresponding to the distance sensing result according to the counting values.

7. The light sensor as claimed in claim 2 , wherein the counting circuit further comprises:

a plurality of delay units, wherein a plurality of first terminals of the delay units are coupled to the second terminal of the second switches;

a plurality of flip-flops, wherein a plurality of clock signal input terminals of the flip-flops are coupled to the second terminal of the second switches, and a plurality of data input terminals of the flip-flops are coupled to a reference voltage;

a plurality of first AND gates, wherein a plurality of first input terminals of the first AND gates are coupled to a plurality of data output terminals of the flip-flops;

a plurality of inverters, wherein a plurality of input terminals of the inverters are respectively coupled to a a plurality of data output terminals of the inverters at a next level, and a plurality of output terminals of the inverters are coupled to a plurality of second input terminals of the first AND gates; and

a plurality of second AND gates, wherein a plurality of first input terminals of the second AND gates are coupled to a plurality of data output terminals of the first AND gates, a plurality of second input terminals of the second AND gates are coupled a plurality of second terminals of the delay units, and a plurality of output terminals of the second AND gates are coupled to the counting units.

8. The light sensor as claimed in claim 7 , wherein at least part of a plurality of turn-on periods of the second switching signals are partially overlapped.

9. The light sensor as claimed in claim 1 , further comprising at least another sensing sub-pixel, wherein the sensing sub-pixel and the at least another sensing sub-pixel belong to a same pixel, and the sensing sub-pixel and the at least another sensing sub-pixel are sequentially exposed during a sensing period.

10. The light sensor as claimed in claim 9 , wherein the sensing sub-pixel and the at least another sensing sub-pixel are partially overlapped during a plurality of exposure periods in the sensing period.

11. A ranging method, comprising:

operating a diode of a sensing sub-pixel in a Geiger mode or an avalanche linear mode;

emitting ranging light by a light source;

sensing reflected light corresponding to the ranging light through the sensing sub-pixel; and

when a time-to-digital converter receives a sensing signal provided by the sensing sub-pixel, generating a plurality of counting values according to the sensing signal through a plurality of counting units of a counting circuit, wherein the counting values are histogram data corresponding to a distance sensing result.

12. The ranging method as claimed in claim 11 , wherein the time-to-digital converter further comprises a controller, a first switch, and a plurality of second switches,

wherein a first terminal of the first switch is coupled to the sensing sub-pixel, a second terminal of the first switch is coupled to a first terminal of the second switches, and a second terminal of the second switches is coupled to the counting units,

wherein the counting circuit outputs a first switching signal to the first switch, and the controller outputs a plurality of second switching signals to control the second switches,

wherein when the sensing sub-pixel provides the sensing signal, the first switch is turned on and at least one of the second switches is turned on, so that the sensing signal is written into one of the counting units,

wherein the sensing signal is a single photon sensing signal.

13. The ranging method as claimed in claim 12 , wherein the second switches are coupled to form a tree structure.

14. The ranging method as claimed in claim 12 , wherein a plurality of signal transmission paths respectively between the counting units and the first switch are sequentially closed in different periods.

15. The ranging method as claimed in claim 12 , wherein the counting units are respectively an up counter.

16. The ranging method as claimed in claim 12 , wherein the counting units output the counting values of a counting result of a plurality of single photon sensing signals of the sensing signal during a sensing period, so that the time-to-digital converter generates the histogram data corresponding to the distance sensing result according to the counting values.

17. The ranging method as claimed in claim 12 , wherein the counting circuit further comprises:

a plurality of delay units, wherein a plurality of first terminals of the delay units are coupled to the second terminal of the second switches;

a plurality of flip-flops, wherein a plurality of clock signal input terminals of the flip-flops are coupled to the second terminal of the second switches, and a plurality of data input terminals of the flip-flops are coupled to a reference voltage;

a plurality of first AND gates, wherein a plurality of first input terminals of the first AND gates are coupled to a plurality of data output terminals of the flip-flops;

a plurality of inverters, wherein a plurality of input terminals of the inverters are respectively coupled to a plurality of data output terminals of the inverters at a next level, and a plurality of output terminals of the inverters are coupled to a plurality of second input terminals of the first AND gates; and

a plurality of second AND gates, wherein a plurality of first input terminals of the second AND gates are coupled to a plurality of data output terminals of the first AND gates, a plurality of second input terminals of the second AND gates are coupled a plurality of second terminals of the delay units, and a plurality of output terminals of the second AND gates are coupled to the counting units.

18. The ranging method as claimed in claim 17 , wherein at least part of a plurality of turn-on periods of the second switching signals are partially overlapped.

19. The ranging method as claimed in claim 11 , further comprising at least another sensing sub-pixel, wherein the sensing sub-pixel and the at least another sensing sub-pixel belong to a same pixel, and the sensing sub-pixel and the at least another sensing sub-pixel are sequentially exposed during a sensing period.

20. The ranging method as claimed in claim 19 , wherein the sensing sub-pixel and the at least another sensing sub-pixel are partially overlapped during a plurality of exposure periods in the sensing period.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2021
From: YIN, PING-HUNG; WANG, JIA-SHYANG
To: GUANGZHOU TYRAFOS SEMICONDUCTOR TECHNOLOGIES CO., LTD
Reel/Frame 056750/0066 →
Continuity (3)
Provisional Application 63058502 · Jul 30, 2020
Provisional Application 63050120 · Jul 10, 2020
Related Publication 20220011412A1 · Jan 13, 2022
Cited By (1)
US 12,418,732