IP Library Granted Patent US 11,955,089
Granted Patent B2
US 11,955,089 · App. 17/680,956 · Granted Apr 9, 2024

Display substrate and display device

Inventors: Zhidong Yuan (Beijing, CN); Yongqian Li (Beijing, CN); Can Yuan (Beijing, CN); Pan Xu (Beijing, CN)
Assignees: HEFEI BOE JOINT TECHNOLOGY CO., LTD; BOE TECHNOLOGY GROUP CO., LTD.
G09G3/3275H10K59/131G09G2310/061
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Quick Facts
Patent No.
US 11,955,089
App. No.
17/680,956
Granted
Apr 9, 2024
Kind
B2
Abstract

Provided is a display substrate. The display substrate includes two pixels arranged along a first direction and adjacent to each other on a base substrate, and a pixel circuit in each of the two pixels includes a drive transistor, a first reset transistor, and a second reset transistor. A display device is also provided.

Claims (36)

1. A display substrate, comprising:

a base substrate;

a first pixel and a second pixel disposed on the base substrate, wherein the first pixel and the second pixel are arranged along a first direction and are adjacent, and both the first pixel and the second pixel comprise a pixel circuit and a light emitting element, the pixel circuit comprising a drive transistor, a first reset transistor, and a second reset transistor; wherein

the first reset transistor is coupled to a first reset control line, a first reset signal line, and a gate of the drive transistor, and the first reset transistor is configured to, in response to a first reset control signal provided by the first reset control line, transmit a first reset signal provided by the first reset signal line to the gate of the drive transistor to reset the gate of the drive transistor; and

the second reset transistor is coupled to a second reset control line, a second reset signal line, and a first electrode of the light emitting element, and the second reset transistor is configured to, in response to a second reset control signal provided by the second reset control line, transmit a second reset signal provided by the second reset signal line to the first electrode of the light emitting element to reset the first electrode of the light emitting element;

wherein the first reset signal line comprises a first portion extending along a second direction, and the first reset transistors, the second reset transistors, and the drive transistors in the first pixel and in the second pixel are arranged symmetrically along a symmetry axis of the first portion respectively, the second direction being a row direction, and the second direction being intersected with the first direction;

the second reset signal line comprises a second portion extending along the second direction; the first reset transistors, the second reset transistors, and the drive transistors in the first pixel and in the second pixel are arranged symmetrically along a symmetry axis of the second portion respectively;

the first reset control line extends along the second direction, and the first reset control line coupled to the pixel circuit in the first pixel and the first reset control line coupled to the pixel circuit in the second pixel are arranged symmetrically along the symmetry axis of the first portion;

the second reset control line extends along the second direction, and the second reset control line coupled to the pixel circuit in the first pixel and the second reset control line coupled to the pixel circuit in the second pixel are arranged symmetrically along the symmetry axis of the second portion; and

the symmetry axis of the first portion is overlapped with the symmetry axis the second portion.

2. The display substrate according to claim 1 , wherein the pixel circuit further comprises: a light emitting control transistor;

wherein the light emitting control transistor is coupled to a light emitting control line, a first power terminal, and a first electrode of the drive transistor, and the light emitting control transistor is configured to, in response to a light emitting control signal provided by the light emitting control line, transmit a first power signal provided by the first power terminal to the first electrode of the drive transistor; and

a second electrode of the drive transistor is coupled to the first electrode of the light emitting element, a second electrode of the light emitting element is coupled to a second power terminal, the drive transistor is configured to transmit a light emitting drive signal to the first electrode of the light emitting element based on a potential of the gate of the drive transistor and a potential of the first electrode of the drive transistor, and the light emitting element is configured to emit light based on the light emitting drive signal and a second power signal provided by the second power terminal.

3. The display substrate according to claim 2 , wherein the light emitting control transistor in the pixel circuit in the first pixel and the light emitting control transistor in the pixel circuit in the second pixel are the same transistor; and

the light emitting control transistor is disposed between the second reset signal line coupled to the pixel circuit in the first pixel and the second reset signal line coupled to the pixel circuit in the second pixel.

4. The display substrate according to claim 3 , wherein the light emitting control line extends along the second direction, and both the symmetry axis of the first portion and the symmetry axis of the second portion are overlapped with the light emitting control line.

5. The display substrate according to claim 2 , wherein the pixel circuit further comprises: a data write transistor,

wherein the data write transistor is coupled to a gate line, a data line, and the drive transistor, and the data write transistor is configured to transmit a data signal provided by the data line to the drive transistor in response to a gate drive signal provided by the gate line.

6. The display substrate according to claim 5 , wherein the data write transistor in the first pixel and the data write transistor in the second pixel are arranged symmetrically along the symmetry axis of the first portion.

7. The display substrate according to claim 5 , wherein the gate line extends along the second direction; and the gate line coupled to the pixel circuit in the first pixel and the gate line coupled to the pixel circuit in the second pixel are arranged symmetrically along the symmetry axis of the first portion.

8. The display substrate according to claim 5 , wherein the data line extends along the first direction.

9. The display substrate according to claim 5 , wherein the first reset signal line, the first reset control line, the gate line, the second reset control line, the second reset signal line, and the light emitting control line coupled to the pixel circuit in one of the first pixel and the second pixel are arranged sequentially along a direction going close to the other one of the first pixel and the second pixel.

10. The display substrate according to claim 9 , wherein in the pixel circuit in one of the first pixel and the second pixel, the first reset transistor, the data write transistor, the drive transistor, the second reset transistor, and the light emitting control transistor are sequentially arranged along the direction going close to the other one of the first pixel and the second pixel; and

the first reset transistor, the data write transistor, the drive transistor, and the second reset transistor are disposed between the first reset signal line and the second reset signal line.

11. A display device comprising: a power supply component, and a display substrate,

wherein the power supply component is coupled to the display substrate, and is configured to supply power to the display substrate; and

the display substrate comprises:

a base substrate;

a first pixel and a second pixel disposed on the base substrate, wherein the first pixel and the second pixel are arranged along a first direction and are adjacent, and both the first pixel and the second pixel comprise a pixel circuit and a light emitting element, the pixel circuit comprising a drive transistor, a first reset transistor, and a second reset transistor; wherein

the first reset transistor is coupled to a first reset control line, a first reset signal line, and a gate of the drive transistor, and the first reset transistor is configured to, in response to a first reset control signal provided by the first reset control line, transmit a first reset signal provided by the first reset signal line to the gate of the drive transistor to reset the gate of the drive transistor; and

the second reset transistor is coupled to a second reset control line, a second reset signal line, and a first electrode of the light emitting element, and the second reset transistor is configured to, in response to a second reset control signal provided by the second reset control line, transmit a second reset signal provided by the second reset signal line to the first electrode of the light emitting element to reset the first electrode of the light emitting element;

wherein the first reset signal line comprises a first portion extending along a second direction, and the first reset transistors, the second reset transistors, and the drive transistors in the first pixel and in the second pixel are arranged symmetrically along a symmetry axis of the first portion respectively, the second direction being a row direction, and the second direction being intersected with the first direction;

the second reset signal line comprises a second portion extending along the second direction; the first reset transistors, the second reset transistors, and the drive transistors in the first pixel and in the second pixel are arranged symmetrically along a symmetry axis of the second portion respectively;

the first reset control line extends along the second direction, and the first reset control line coupled to the pixel circuit in the first pixel and the first reset control line coupled to the pixel circuit in the second pixel are arranged symmetrically along the symmetry axis of the first portion;

the second reset control line extends along the second direction, and the second reset control line coupled to the pixel circuit in the first pixel and the second reset control line coupled to the pixel circuit in the second pixel are arranged symmetrically along the symmetry axis of the second portion; and

the symmetry axis of the first portion is overlapped with the symmetry axis the second portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2022
From: YUAN, ZHIDONG; LI, YONGQIAN; YUAN, CAN; XU, PAN
To: HEFEI BOE JOINT TECHNOLOGY CO., LTD; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 059103/0669 →
Priority Claims (1)
CN 202010707527.3 · Jul 21, 2020 · national
Continuity (2)
Continuation In Part PCTCN2021099017 · Jun 8, 2021
Related Publication 20220180816A1 · Jun 9, 2022