Interposer structures and methods for 2.5D and 3D packaging
Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.
1. A device comprising:
an extension platform, the extension platform having at least one opening and a recess-step portion;
an interposer in the opening in the extension platform, wherein the interposer is separated by a space from the extension platform and is at least partially encircled by the extension platform;
at least one bridge coupling the extension platform and the interposer; and
a substrate, wherein the interposer is coupled to the substrate.
2. The device of claim 1 , further comprising the recess-step portion having at least a third semiconductor device positioned thereon.
3. The device of claim 2 , further comprising the recess-step portion having a first conductive via coupled to the third semiconductor device.
4. The device of claim 2 , further comprising the third semiconductor device on the recess-step portion is coupled by a second conductive via to the substrate.
5. The device of claim 1 , wherein the at least one opening in the extension platform further comprises two openings with a section of the recess-step portion positioned therebetween.
6. The device of claim 5 , further comprising the section of the recess-step portion having a third conductive via coupled to at least a fourth semiconductor device.
7. The device of claim 5 , further comprising each of the two openings having a first and second interposers positioned, respectively, therein.
8. The device of claim 1 , further comprising a polymeric material filling the space between the interposer and the extension platform.
9. The device of claim 1 , further comprising at least a first semiconductor chip coupled to the interposer.
10. The device of claim 9 , further comprising at least a second semiconductor chip coupled to the extension platform.
11. The device of claim 1 , further comprising a connecting chip extending from an encircling side of the extension platform over the interposer and extends to another encircling side of the extension platform.
12. The device of claim 1 , further comprising a first metallization layer on the interposer and a second metallization layer on the extension platform.
13. The device of claim 1 , further comprising a shield layer on the extension platform.
14. The device of claim 1 , further comprising the bridge having a bridge metallization layer for coupling the extension platform and the interposer.
15. The device of claim 14 , wherein the bridge further comprises a semiconductor device with metallization layers that carry electrical signals and/or delivers power, wherein the semiconductor device is a passive device or an active device.
16. A method comprising:
providing a platform material and patterning to form an extension platform having at least one opening and a recess-step portion;
positioning an interposer in the opening, separated by a space from and encircled by the extension platform;
filling the space between the interposer and the extension platform with a polymeric material;
positioning a bridge between the extension platform and the interposer, wherein the bridge couples the extension platform and the interposer;
positioning a first semiconductor chip over the interposer and coupling the first semiconductor chip to the interposer; and
positioning a second semiconductor chip over the extension platform and coupling the second semiconductor chip to the extension platform.
17. The method of claim 16 , further comprises:
forming at least one conductive via in the recess-step portion; and
positioning at least a third semiconductor device on the recess-step portion.
18. A computing device comprising:
a circuit board; and
a semiconductor package, wherein the semiconductor package further comprises:
a substrate having top and bottom surfaces, wherein the bottom surface of the substrate is coupled to the circuit board;
an extension platform positioned over the top surface of the substrate, the extension platform having at least one opening and a recess-step portion having at least a third semiconductor device thereon;
an interposer in the opening and separated by a space from the extension platform, wherein the interposer is coupled to the top surface of the substrate;
a polymeric material filling the space between the interposer and the extension platform; a bridge coupling the extension platform and the interposer;
a first plurality of semiconductor chips coupled to the interposer; and
a second plurality of second semiconductor chips coupled to the extension platform, wherein the semiconductor package is coupled to the circuit board.