Semiconductor device and semiconductor circuit

1. A semiconductor device comprising:

a transistor region including

a semiconductor layer having a first face and a second face opposed to the first face,

a first semiconductor region of a first conductivity type provided in the semiconductor layer,

a second semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the first semiconductor region and the first face,

a third semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first face,

a fourth semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the third semiconductor region and the first face,

a fifth semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the third semiconductor region and the first face, and having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the third semiconductor region,

a first trench provided on a side of the first face in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region,

a first gate electrode provided in the first trench,

a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region,

a second trench provided on a side of the first face in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region;

a second gate electrode provided in the second trench,

a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region,

a third trench provided on a side of the first face in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region,

a third gate electrode provided in the third trench,

a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region,

a first electrode provided on a side of the first face with respect to the semiconductor layer and in contact with the fourth semiconductor region and the fifth semiconductor region, and

a second electrode provided on a side of the second face with respect to the semiconductor layer and in contact with the first semiconductor region;

a diode region including

the semiconductor layer,

the second semiconductor region,

a sixth semiconductor region of a second conductivity type provided in the semiconductor layer, provided between the second semiconductor region and the second face, and having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second semiconductor region,

a seventh semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first face,

an eighth semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the seventh semiconductor region and the first face, and having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the seventh semiconductor region,

a fifth trench provided on a side of the first face in the semiconductor layer and in contact with the second semiconductor region and the seventh semiconductor region,

a conductive layer provided in the fifth trench,

an insulating film provided between the conductive layer and the second semiconductor region and between the conductive layer and the seventh semiconductor region,

the first electrode in contact with the eighth semiconductor region, and

the second electrode in contact with the sixth semiconductor region;

a boundary region provided between the transistor region and the diode region, the boundary region including

the semiconductor layer,

the second semiconductor region,

a ninth semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the first face,

a tenth semiconductor region of a second conductivity type provided in the semiconductor layer and provided between the ninth semiconductor region and the first face,

an eleventh semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the ninth semiconductor region and the first face, and having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the ninth semiconductor region,

a fourth trench provided on a side of the first face in the semiconductor layer and in contact with the second semiconductor region, the ninth semiconductor region, and the tenth semiconductor region,

a fourth gate electrode provided in the fourth trench,

a fourth gate insulating film provided between the fourth gate electrode and the second semiconductor region, between the fourth gate electrode and the ninth semiconductor region, and between the fourth gate electrode and the tenth semiconductor region,

the first electrode in contact with the tenth semiconductor region and the eleventh semiconductor region, and

the second electrode;

a first electrode pad provided on a side of the first face with respect to the semiconductor layer and electrically connected to the first gate electrode;

a second electrode pad provided on a side of the first face with respect to the semiconductor layer and electrically connected to the second gate electrode; and

a third electrode pad provided on a side of the first face with respect to the semiconductor layer and electrically connected to the third gate electrode and the fourth gate electrode.

2. The semiconductor device according to claim 1 , wherein the first conductivity type impurity concentration of the ninth semiconductor region is lower than the first conductivity type impurity concentration of the third semiconductor region.

3. The semiconductor device according to claim 1 , wherein an occupation area ratio of the eleventh semiconductor region on the first face of the boundary region is smaller than the occupation area ratio of the fifth semiconductor region on the first face of the transistor region.

4. The semiconductor device according to claim 1 , wherein an occupation area ratio of the fourth gate electrode in a cross section parallel to the first face of the boundary region is greater than the occupation area ratio of the third gate electrode in the cross section of the transistor region.

5. The semiconductor device according to claim 1 , wherein the first semiconductor region is provided between the ninth semiconductor region and the second face.

6. The semiconductor device according to claim 1 , further comprising a twelfth semiconductor region of a second conductivity type provided in the semiconductor layer, provided between the second semiconductor region and the third semiconductor region, provided between the second semiconductor region and the ninth semiconductor region, and having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second semiconductor region.

7. The semiconductor device according to claim 1 , wherein a depth of the ninth semiconductor region in a direction from the first face toward the second face is smaller than a depth of the third semiconductor region in the direction from the first face toward the second face.

8. The semiconductor device according to claim 1 , wherein the diode region further includes a thirteenth semiconductor region of a first conductivity type provided in the semiconductor layer and provided between the second semiconductor region and the second face, and

the second electrode is in contact with the thirteenth semiconductor region.

9. The semiconductor device according to claim 1 , wherein the conductive layer is electrically connected to the first electrode.

10. The semiconductor device according to claim 1 , wherein:

a first turn-on voltage is applied to the first electrode pad ( 104 );

a second turn-on voltage is applied to the second electrode pad ( 105 );

a third turn-on voltage is applied to the third electrode pad ( 106 );

a third turn-off voltage is applied to the third electrode pad, after the first turn-on voltage is applied to the first electrode pad ( 104 ), after the second turn-on voltage is applied to the second electrode pad, and after the third turn-on voltage is applied to the third electrode pad;

a second turn-off voltage is applied to the second electrode pad after the third turn-off voltage is applied to the third electrode pad; and

a first turn-off voltage is applied to the first electrode pad after the second turn-off voltage is applied to the second electrode pad.

11. A semiconductor circuit comprising:

the semiconductor device according to claim 1 ; and

a control circuit configure to:

drive the semiconductor device, apply a first turn-on voltage to the first electrode pad, a second turn-on voltage to the second electrode pad, and a third turn-on voltage to the third electrode pad;

apply a third turn-off voltage to the third electrode pad after applying the first turn-on voltage to the first electrode pad, the second turn-on voltage to the second electrode pad, and the third turn-on voltage to the third electrode pad;

apply a second turn-off voltage to the second electrode pad after applying the third turn-off voltage to the third electrode pad; and

apply a first turn-off voltage to the first electrode pad after applying the second turn-off voltage to the second electrode pad.