IP Library › Granted Patent US 11,955,522
Granted Patent B2
US 11,955,522 · App. 16/789,682 · Granted Apr 9, 2024

Semiconductor structure and method of forming the same

Inventors: Cheng-Wei Chou (Taoyuan, TW); Shin-Cheng Lin (Tainan, TW); Yung-Fong Lin (Taoyuan, TW)
Assignee: Vanguard International Semiconductor Corporation
H01L29/408H01L21/0217H01L21/02186H01L21/28575H01L23/291H01L23/3192H01L29/2003H01L29/205H01L29/452H01L29/66462H01L29/7786H01L29/7787
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Quick Facts
Patent No.
US 11,955,522
App. No.
16/789,682
Granted
Apr 9, 2024
Kind
B2
Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a source structure, and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure are disposed on the passivation layer.

Claims (34)

1. A semiconductor structure, comprising:

a substrate;

a buffer layer disposed on the substrate;

a barrier layer disposed on the buffer layer;

a dielectric layer disposed on the barrier layer;

a protection layer disposed on the dielectric layer, wherein the protection layer is a multilayer structure, and wherein the protection layer comprises:

a material layer, wherein the material layer comprises SiN; and

a passivation layer disposed on the material layer; and

a source structure and a drain structure both disposed directly above the protection layer, wherein sidewalls of the protection layer are aligned with uppermost-outermost opposing sidewalls of each of the source structure and the drain structure and aligned with lowermost-outermost opposing sidewalls of each of the source structure and the drain structure, and the protection layer is above the dielectric layer and below one of the source structure and the drain structure, and wherein the protection layer is solely under the source structure and the drain structure,

wherein a vertical projection of an entirety of protrusions of the source structure and of protrusions of an entirety of the drain structure on the substrate and a vertical projection of an entirety of the protection layer on the substrate have a same entire projection area.

2. The semiconductor structure as claimed in claim 1 , wherein the source structure and the drain structure are in direct contact with the buffer layer.

3. The semiconductor structure as claimed in claim 1 , further comprising a gate structure disposed between the source structure and the drain structure.

4. The semiconductor structure as claimed in claim 3 , wherein the gate structure comprises:

a gate layer; and

a gate electrode layer disposed on the gate layer.

5. The semiconductor structure as claimed in claim 4 , wherein a material of the gate electrode layer comprises a metal nitride.

6. The semiconductor structure as claimed in claim 5 , wherein the material of the gate electrode layer comprises titanium nitride.

7. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a buffer layer on the substrate;

forming a barrier layer on the buffer layer;

forming a dielectric layer on the barrier layer;

forming a protection layer on the dielectric layer, wherein the protection layer is a multilayer structure, and wherein the protection layer comprises:

a material layer, wherein the material layer comprises SiN; and

a passivation layer disposed on the material layer; and

forming a source structure and a drain structure both directly above the protection layer, wherein sidewalls of the protection layer are aligned with uppermost-outermost opposing sidewalls of each of the source structure and the drain structure and aligned with lowermost-outermost opposing sidewalls of each of the source structure and the drain structure, and the protection layer is above the dielectric layer and below one of the source structure and the drain structure, and wherein the protection layer is solely under the source structure and the drain structure,

wherein a vertical projection of an entirety of protrusions of the source structure and of protrusions of an entirety of the drain structure on the substrate and a vertical projection of an entirety of the protection layer on the substrate have a same entire projection area.

8. The method of forming a semiconductor structure as claimed in claim 7 , wherein the source structure and the drain structure are in direct contact with the buffer layer.

9. The method of forming a semiconductor structure as claimed in claim 7 , further comprising forming a gate structure between the source structure and the drain structure.

10. The method as claimed in claim 9 , wherein the gate structure comprises:

a gate layer; and

a gate electrode layer disposed on the gate layer.

11. The method as claimed in claim 10 , wherein a material of the gate electrode layer comprises a metal nitride.

12. The method as claimed in claim 11 , wherein the material of the gate electrode layer comprises titanium nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2020
From: CHOU, CHENG-WEI; LIN, SHIN-CHENG; LIN, YUNG-FONG
To: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
Reel/Frame 051815/0222 →
Continuity (1)
Related Publication 20210257467A1 · Aug 19, 2021
Cited By (1)
US 12,740,082