Data storage cell, memory, and memory fabrication method thereof
The invention discloses a memory fabrication method. The memory fabrication method includes forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, and forming a plurality of conductive lines. The plurality of data storage cells are arranged in an array. Each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines. Each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines.
1. A memory fabrication method, comprising:
forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, wherein the plurality of data storage cells are arranged in an array; and
forming a plurality of conductive lines, wherein each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines, and each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines,
wherein the plurality of conductive lines comprise a plurality of first conductive lines and a plurality of second conductive lines, the plurality of first conductive lines are perpendicular to the plurality of second conductive lines, one of the plurality of first conductive lines overlapping one of the plurality of second conductive lines are staggered and non-aligned with another of the plurality of first conductive lines overlapping another of the plurality of second conductive lines.
2. The memory fabrication method of claim 1 , further comprising:
forming a plurality of bit lines, wherein the plurality of bit lines are parallel to the plurality of first conductive lines, and at least four adjacent ones of the plurality of bit lines are located between two adjacent and aligned ones of the plurality of first conductive lines.
3. The memory fabrication method of claim 1 , further comprising:
forming a plurality of source lines, wherein the plurality of source lines are parallel to the plurality of first conductive lines, and two of the plurality of first conductive lines respectively adjacent to opposite sides of one of the plurality of source lines are staggered and non-aligned.
4. The memory fabrication method of claim 1 , wherein each of the plurality of first conductive lines is electrically connected to and contacts two of the plurality of gate electrode lines.
5. The memory fabrication method of claim 1 , wherein a first thickness of each of the plurality of gate electrode lines is 0.5 to 2 times as large as a second thickness of each of the plurality of first conductive lines, a first width of each of the plurality of gate electrode lines is 0.5 to 1 times a second width of each of the plurality of first conductive lines, and the first width of each of the plurality of gate electrode lines is 0.1 to 0.2 times as large as a length of each of the plurality of first conductive lines.
6. The memory fabrication method of claim 1 , wherein the plurality of second conductive lines are respectively word lines, and the plurality of second conductive lines are parallel to the plurality of gate electrode lines.
7. The memory fabrication method of claim 1 , wherein a second pitch between two adjacent ones of the plurality of second conductive lines is more than or equal to twice a first pitch between two adjacent ones of the plurality of gate electrode lines, and a gap width between two adjacent ones of the plurality of gate electrode lines is less than or equal to a second width of each of the plurality of second conductive lines.
8. The memory fabrication method of claim 1 , wherein a first thickness of each of the plurality of gate electrode lines is 0.1 to 0.5 as large as a second thickness of each of the plurality of second conductive lines, and a first width of each of the plurality of gate electrode lines is 0.2 to 0.5 times as large as a second width of each of the plurality of second conductive lines.
9. The memory fabrication method of claim 1 , wherein each of the plurality of second conductive lines completely overlaps two of the plurality of gate electrode lines.
10. A memory, comprising:
a plurality of data storage cells, arranged in an array, wherein a plurality of gates of the plurality of data storage cells respectively constitute a plurality of gate electrode lines; and
a plurality of conductive lines, wherein each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines, and each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines,
wherein the plurality of conductive lines comprise a plurality of first conductive lines and a plurality of second conductive lines, the plurality of first conductive lines are perpendicular to the plurality of second conductive lines, one of the plurality of first conductive lines overlapping one of the plurality of second conductive lines are staggered and non-aligned with another of the plurality of first conductive lines overlapping another of the plurality of second conductive lines.
11. The memory of claim 10 , further comprising:
a plurality of bit lines, wherein the plurality of bit lines are parallel to the plurality of first conductive lines, and at least four adjacent ones of the plurality of bit lines are located between two adjacent and aligned ones of the plurality of first conductive lines.
12. The memory of claim 10 , further comprising:
a plurality of source lines, wherein the plurality of source lines are parallel to the plurality of first conductive lines, and two of the plurality of first conductive lines respectively adjacent to opposite sides of one of the plurality of source lines are staggered and non-aligned.
13. The memory of claim 10 , wherein each of the plurality of first conductive lines is electrically connected to and contacts two of the plurality of gate electrode lines.
14. The memory of claim 10 , wherein a first thickness of each of the plurality of gate electrode lines is 0.5 to 2 times as large as a second thickness of each of the plurality of first conductive lines, a first width of each of the plurality of gate electrode lines is 0.5 to 1 times a second width of each of the plurality of first conductive lines, and the first width of each of the plurality of gate electrode lines is 0.1 to 0.2 times as large as a length of each of the plurality of first conductive lines.
15. The memory of claim 10 , wherein the plurality of second conductive lines are respectively word lines, and the plurality of second conductive lines are parallel to the plurality of gate electrode lines.
16. The memory of claim 10 , wherein a second pitch between two adjacent ones of the plurality of second conductive lines is more than or equal to twice a first pitch between two adjacent ones of the plurality of gate electrode lines, and a gap width between two adjacent ones of the plurality of gate electrode lines is less than or equal to a second width of each of the plurality of second conductive lines.
17. The memory of claim 10 , wherein a first thickness of each of the plurality of gate electrode lines is 0.1 to 0.5 as large as a second thickness of each of the plurality of second conductive lines, and a first width of each of the plurality of gate electrode lines is 0.2 to 0.5 times as large as a second width of each of the plurality of second conductive lines.
18. The memory of claim 10 , wherein each of the plurality of second conductive lines completely overlaps two of the plurality of gate electrode lines.