Phase-change memory cell having a compact structure
A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
1. A memory, comprising:
a semiconductor substrate;
a first insulating layer on the semiconductor substrate;
an active layer of a semiconductor material on the first insulating layer;
a control gate of a first selection transistor on the active layer and having a lateral flank;
a second insulating layer covering the lateral flank of the control gate;
a first conduction region and a second conduction region of the first selection transistor in the active layer;
a trench in the active layer and defined on a first side by a first lateral flank of the active layer and reaching the first insulating layer;
a heater layer of resistive material in the trench covering the first lateral flank of the active layer and in contact with the second insulating layer; and
a layer of a variable resistance material having a bottom surface above the trench and higher than a top of the second insulating layer, wherein the bottom surface is in contact with the heater layer, electrically coupled to the first conduction region, and the heater layer of resistive material is configured to heat the layer of the variable resistance material.
2. The memory of claim 1 , wherein the heater layer of resistive material is configured to cause the layer of variable resistance material to change phase between a non-conductive amorphous phase and a conductive crystalline phase.
3. The memory of claim 1 , wherein the layer of variable resistance material contacts an upper portion of the heater layer of resistive material and extends longitudinally in a plane parallel to the surface of the substrate.
4. The memory of claim 3 , further comprising a dielectric trench isolation formed under the layer of variable resistive material and covering a lateral flank of the heater layer of resistive material.
5. The memory of claim 1 , wherein:
the second insulating layer extends above the control gate;
the heater layer of resistive material extends upwardly from the trench along the second insulating layer and reaches a top surface of the second insulating layer; and
the layer of variable resistance material is positioned above the second insulating layer.
6. The memory of claim 1 , wherein the heater layer of resistive material extends in the trench and contacts a first contact portion of the layer of variable resistance material.
7. The memory of claim 6 , further comprising a second heater layer of resistive material extending in the trench, covering a second lateral flank of the active layer, and contacting a second contact portion of the layer of variable resistance material.
8. The memory of claim 7 , further comprising:
a control gate of a second selection transistor on the active layer and having a lateral flank;
a third insulating layer covering the lateral flank of the control gate of the second selection transistor; and
first and second conduction regions of the second selection transistor in the active layer, wherein the third insulating layer contacts the first conduction region of the second selection transistor.