Skew matching in a die-to-die interface
A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.
1. A semiconductor package for skew matching in a die-to-die interface, comprising:
a first die;
a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is equidistant to a corresponding connection point of a second plurality of connection points of the second die, wherein a transmit block of the first die is linearly aligned with a receive block of the second die and a transmit block of the second die is linearly aligned with a receive block of the first die; and
a plurality of connection paths of a same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.
2. The semiconductor package of claim 1 , wherein a layout of the first plurality of connection points is different from a layout of the second plurality of connection points.
3. The semiconductor package of claim 1 , wherein an interface between the first die and the second die includes a bridge die.
4. The semiconductor package of claim 1 , further comprising a clock coupled to the first die and the second die.
5. The semiconductor package of claim 4 , wherein the first plurality of connection points and the second plurality of connection points each comprise a first subset of connection points for data transfer and a second subset of connection points for clocking.
6. The semiconductor package of claim 5 , wherein the first die and the second die each provide a respective source-synchronous clocking signal with a respective data signal.
7. The semiconductor package of claim 6 , wherein the respective source-synchronous clocking signal is in quadrature with the respective data signal.
8. A method of skew matching in a die-to-die interface, the method comprising:
aligning a first die with a second die such that each connection point of a first plurality of connection points of the first die is equidistant to a corresponding connection point of a second plurality of connection points of the second die, wherein, after aligning the first die with the second die, a transmit block of the first die is linearly aligned with a receive block of the second die and a transmit block of the second die is linearly aligned with a receive block of the first die; and
coupling each connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points using a connection path, wherein each of the connection paths comprises a same length.
9. The method of claim 8 , wherein a layout of the first plurality of connection points is different from a layout of the second plurality of connection points.
10. The method of claim 8 , wherein an interface between the first die and the second die includes a bridge die.
11. The method of claim 9 , further comprising coupling a clock to the first die and the second die.
12. The method of claim 11 , wherein the first plurality of connection points and the second plurality of connection points each comprise a first subset of connection points for data transfer and a second subset of connection points for clocking.
13. The method of claim 12 , wherein coupling the clock the first die and the second die comprises configuring the first die and the second die to each provide a respective source-synchronous clocking signal with a respective data signal.
14. The method of claim 13 , wherein the respective source-synchronous clocking signal is in quadrature with the respective data signal.
15. An apparatus for skew matching in a die-to-die interface, comprising:
computer memory;
a semiconductor package operatively coupled to the computer memory, comprising:
a first die;
a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is equidistant to a corresponding connection point of a second plurality of connection points of the second die, wherein a transmit block of the first die is linearly aligned with a receive block of the second die and a transmit block of the second die is linearly aligned with a receive block of the first die; and
a plurality of connection paths of a same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.
16. The apparatus of claim 15 , wherein a layout of the first plurality of connection points is different from a layout of the second plurality of connection points.
17. The apparatus of claim 15 , wherein an interface between the first die and the second die includes a bridge die.
18. The apparatus of claim 15 , wherein the semiconductor package further comprises a clock coupled to the first die and the second die.
19. The apparatus of claim 18 , wherein the first plurality of connection points and the second plurality of connection points each comprise a first subset of connection points for data transfer and a second subset of connection points for clocking.
20. The apparatus of claim 19 , wherein the first die and the second die each provide a respective source-synchronous clocking signal with a respective data signal.