IP Library › Granted Patent US 11,961,779
Granted Patent B2
US 11,961,779 · App. 17/331,945 · Granted Apr 16, 2024

3DIC packaging with hot spot thermal management features

Inventors: Wensen Hung (Zhubei, TW); Szu-Po Huang (Taichung, TW); Hsiang-Fan Lee (Hsinchu, TW); Kim Hong Chen (Fremont, CA); Chi-Hsi Wu (Hsinchu, TW); Shin-Puu Jeng (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC).
H01L23/36H01L23/04H01L23/10H01L23/3675H01L23/3677H01L23/42H01L23/49822H01L23/49827H01L25/0652H01L25/0657H01L23/49816H01L24/13H01L24/16H01L24/32H01L24/73H01L24/83H01L24/92H01L25/18H01L2224/13025H01L2224/131H01L2224/16145H01L2224/16227H01L2224/29011H01L2224/291H01L2224/2919H01L2224/29294H01L2224/29339H01L2224/32225H01L2224/32245H01L2224/33181H01L2224/33519H01L2224/73204H01L2224/73253H01L2224/81815H01L2224/83191H01L2224/92125H01L2224/92225H01L2225/06513H01L2225/06517H01L2225/06541H01L2225/06568H01L2225/06589H01L2924/1431H01L2924/1432H01L2924/1434H01L2924/1436H01L2924/15311H01L2924/16153H01L2924/16251H01L2924/1679H01L2924/181H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19105
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Quick Facts
Patent No.
US 11,961,779
App. No.
17/331,945
Granted
Apr 16, 2024
Kind
B2
Abstract

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

Claims (32)

1. A package comprising:

a package substrate having a conductive layer and a solder resist on a same side;

a die stack provided over the package substrate;

a thermal interface material (TIM) directly over the conductive layer and contacting the solder resist, wherein the TIM is disposed at a same level as a top surface of the solder resist; and

a heat dissipation feature disposed over the TIM.

2. The package of claim 1 , wherein the heat dissipation feature is adhered to the package substrate by an adhesive material.

3. The package of claim 2 , wherein the adhesive material has a lower thermal conductivity than the thermal interface material.

4. The package of claim 2 , wherein the adhesive material is disposed on opposing sides of the thermal interface material.

5. The package of claim 1 , wherein the conductive layer is a signal, a power, or a ground layer.

6. The package of claim 1 , wherein the conductive layer comprises a dummy feature.

7. The package of claim 1 , wherein the die stack comprises a plurality of memory dies.

8. The package of claim 1 , wherein the conductive layer extends continuously from directly under the die stack to directly under the TIM.

9. The package of claim 1 , wherein the TIM contacts a top surface of the conductive layer.

10. A package comprising:

a package substrate having a conductive layer and a polymer on a same side;

a die stack over the package substrate;

a thermal interface material (TIM) in a region directly above the conductive layer, the TIM being disposed between a first portion of the polymer and a second portion of the polymer, the first portion of the polymer and the second portion of the polymer being on opposing sides of the region; and

a heat dissipation feature over the TIM, the conductive layer, and the polymer.

11. The package of claim 10 , wherein the heat dissipation feature is attached to a top surface of the die stack by a second TIM.

12. The package of claim 10 , wherein the heat dissipation feature is attached to a top surface of the package substrate by an adhesive.

13. The package of claim 12 , wherein the TIM has a higher thermal conductivity than the adhesive.

14. The package of claim 10 , wherein the TIM contacts a sidewall of the first portion of the polymer and a sidewall of the second portion of the polymer.

15. The package of claim 10 , wherein the die stack comprises a plurality of memory dies.

16. A package comprising:

a package substrate having a conductive layer and a polymer on a same side;

a die stack provided over the package substrate;

a thermal interface material (TIM) directly contacting a first sidewall of the polymer and a second sidewall of the polymer; and

a heat dissipation feature disposed above the TIM, wherein the conductive layer extends continuously from directly under the die stack to directly under the TIM.

17. The package of claim 16 , wherein the heat dissipation feature contacts the TIM.

18. The package of claim 16 , wherein the heat dissipation feature is adhered to the package substrate using an adhesive having a lower thermal conductivity than the TIM.

19. The package of claim 18 , wherein the adhesive is disposed on opposing sidewalls of the TIM.

20. The package of claim 16 , wherein the die stack comprises a plurality of memory dies.

Continuity (5)
Continuation 16587463 · Sep 30, 2019
Continuation 16206903 · Nov 30, 2018
Continuation 15676963 · Aug 14, 2017
Continuation 14096952 · Dec 4, 2013
Related Publication 20210287956A1 · Sep 16, 2021