Optoelectronic device with PN junction and trench gate
View Patent ↗The present description concerns an optoelectronic device ( 300 ) including: a vertical stack of first ( 101 ) and second ( 105 ) semiconductor layers forming a PN junction, and of a third conductive layer ( 107 ) arranged on top of and in contact with the surface of the second layer opposite to the first layer; a peripheral trench ( 110 ) crossing the third ( 107 ) and second ( 105 ) layers, said trench laterally delimiting a portion of the third layer ( 107 ) and a portion of the second layer ( 105 ); in said trench ( 110 ), a conductive spacer ( 301 ) in contact with a lateral side of said portion of the third layer ( 107 ); and in said trench ( 110 ), an insulated conductive gate ( 113, 111 ) extending against a lateral side of the conductive spacer ( 301 ) and against a lateral side of said portion of the second layer.
1. Optoelectronic device comprising:
a vertical stack of a first doped semiconductor layer of a first conductivity type, of a second doped semiconductor layer of a second conductivity type forming with the first doped semiconductor layer a PN junction, and of a third conductive layer arranged on top of and in contact with a surface of the second doped semiconductor layer opposite to the first doped semiconductor layer;
a peripheral trench crossing the third conductive layer and the second doped semiconductor layer, said peripheral trench laterally delimiting a portion of the third conductive layer and a portion of the second doped semiconductor layer;
in said peripheral trench, a conductive spacer made of metal and in contact with a lateral side of said portion of the third conductive layer; and
in said peripheral trench, an insulated conductive gate comprising a gate insulator layer extending on top of and in contact with a lateral side of the conductive spacer and on top of and in contact with a lateral side of said portion of the second doped semiconductor layer, and a conductive gate layer arranged on top of and in contact with a surface of the gate insulator layer opposite to the conductive spacer and to said portion of the second doped semiconductor layer.
2. Device according to claim 1 , wherein the conductive spacer is a material different from that of the third layer.
3. Device according to claim 2 , wherein the conductive spacer is made of a metal from the group comprising platinum, nickel, and tungsten.
4. Device according to claim 1 , wherein the third conductive layer is made of aluminum or of silver.
5. Device according to claim 1 , further comprising a connection metallization in contact with the first doped semiconductor layer.
6. Device according to claim 5 , wherein said connection metallization is electrically insulated from the insulated conductive gate.
7. Device according to claim 5 , wherein said connection metallization is electrically connected to the insulated conductive gate.
8. Device according to claim 1 , further comprising an emissive semiconductor layer between the first and second doped semiconductor layers, wherein the peripheral trench crosses the emissive semiconductor layer, said peripheral trench laterally delimiting a portion of the emissive semiconductor layer, and the insulated conductive gate extending against a lateral side of said portion of the emissive semiconductor layer.
9. Device according to claim 1 , wherein each of the first and second dope semiconductor layers is made of a III-N compound.
10. Method of manufacturing an optoelectronic device according to claim 1 , comprising the successive steps of:
a) providing the stack comprising the first doped semiconductor layer, the second doped semiconductor layer, and the third conductive layer;
b) forming the peripheral trench crossing the third conductive layer and stopping on the second doped semiconductor layer, said peripheral trench laterally delimiting said portion of the third conductive layer;
c) forming in said peripheral trench the conductive spacer in contact with the sides of said portion of the third conductive layer;
d) continuing said peripheral trench through the second doped semiconductor layer, said continued peripheral trench laterally delimiting said portion of the second doped semiconductor layer; and
e) forming in said peripheral trench the insulated conductive gate.
11. Method according to claim 10 , further comprising after step d) and before step e), a step of chemical cleaning of the exposed surfaces of the first doped semiconductor layer inside of the peripheral trench.
12. Method according to claim 11 , wherein the step of chemical cleaning is carried out by means of a solution based on potassium hydroxide or of a solution based on tetramethylammonium hydroxide, or of a solution based on tetraethylammonium hydroxide.