Iterative decoding technique for correcting DRAM device failures

1. A memory system comprising:

a plurality of memory components; and

a controller in communication with the plurality of memory components and configured to:

perform error correction code (ECC) decoding on a received word read from the plurality of memory components

comprising:

(i) performing a single decoding attempt to detect one or more random errors in a portion of the received word, the portion corresponding to one memory component within the plurality of memory components, and correct the detected random errors; and

(ii) when the correcting of the detected random errors fails, iteratively performing decoding attempts with each attempt marking symbols in the remaining portions of the received word that correspond respectively to remaining memory components of the plurality of memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.

2. The memory system of claim 1 , wherein the random errors include at least one of bit and symbol errors.

3. The memory system of claim 2 , wherein the marking facilitates correcting the symbols in the remaining portions of the received word.

4. The memory system of claim 1 , wherein the plurality of memory components includes dynamic random access memory (DRAM) devices.

5. The memory system of claim 4 , wherein the memory system is constructed in accordance compute express link (CXL) principles.

6. The memory system of claim 1 , wherein the ECC decoding is performed in each attempt in accordance with at least one of the group including (i) sequentially, (ii) in parallel, and (iii) a combination of sequentially and in parallel.

7. The memory system of claim 1 , wherein the ECC decoding is performed in accordance with Reed Solomon (RS) codes.

8. The memory system of claim 1 , wherein the first plurality of symbols includes at least four symbols.

9. The memory system of claim 3 , wherein one portion of the received word includes data symbols and a remaining portion of the received word includes parity symbols.

10. The memory system of claim 9 , wherein the controller includes an erasure pointer for storing a location of a detected erasure and supplying the location to a syndrome decoder.

11. The memory system of claim 9 , wherein the controller includes a pointer for tracking which symbols where the erasure attempts have been performed.

12. The memory system of claim 10 , wherein the detecting includes (i) identifying an error as an erasure and (ii) withholding supply of corresponding erasure location to the syndrome decoder.

13. The memory system of claim 3 , wherein all of the remaining symbols from the plurality of portions are marked as erasures.

14. A method comprising:

performing, in a controller of a memory system including a plurality of memory components, error correction code (ECC) decoding on a received word read from the plurality of memory components

by (i) performing a single decoding attempt to detect one or more random errors in a portion of the received word, the portion corresponding to one memory component within the plurality of memory components, and correct the detected random errors; and

(ii) when the correcting of the detected random errors fails, iteratively performing decoding attempts with each attempt marking symbols in the remaining portions of the received word that correspond respectively to remaining memory components of the plurality of memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.

15. The method of claim 14 , wherein marking at least one of the remaining symbols as an erasure facilitates correcting symbols in all the remaining memory components within the plurality of memory components; and

wherein the correcting includes (i) incrementing from a first memory component to each of the remaining components within the plurality of memory components and (ii) performing the ECC check on all the symbols on each of the remaining memory components.

16. The method of claim 15 , wherein the plurality of memory components includes dynamic random access memory (DRAM) devices.

17. The method of claim 16 , wherein the memory system is constructed in accordance compute express link (CXL) principles.

18. The method of claim 15 , wherein the ECC decoding is performed in each of the remaining memory components in accordance with at least one of the group including substantially sequentially and substantially in parallel.

19. The method of claim 16 , wherein the ECC decoding is performed in accordance with Reed Solomon (RS) codes.

20. The method of claim 15 , wherein the first plurality of symbols includes at least four symbols.

21. A non-transitory computer readable medium having stored thereon computer executable instructions that, if executed by a computing device, cause the computing device to perform a method for use by a memory controller of a memory system including a plurality of memory components, the method comprising:

performing, in a controller of a memory system including a plurality of memory components, error correction code (ECC) decoding on a received word read from the plurality of memory components

by (i) performing a single decoding attempt to detect one or more random errors in a portion of the received word, the portion corresponding to one memory component within the plurality of memory components, and correct the detected random errors; and

(ii) when the correcting of the detected random errors fails, iteratively performing decoding attempts with each attempt marking symbols in the remaining portions of the received word that correspond respectively to remaining memory components of the plurality of memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.