Solid-state image sensor
A solid-state image sensor includes: an input transistor configured to output, from a drain, a drain voltage according to an input voltage input to a source in a case where the input voltage substantially coincides with a predetermined reference voltage input to a gate; and an output transistor configured to output a signal indicating whether or not a difference between the input voltage input to a source and the drain voltage input to a gate exceeds a predetermined threshold voltage as a comparison result between the input voltage and the reference voltage.
1. An imaging device comprising:
a pixel circuit configured to output a pixel signal;
a pixel signal line coupled to the pixel circuit;
a reference signal generation circuit configured to output a reference signal; and
a comparator including:
a first transistor, wherein a first terminal of the first transistor is coupled to the reference signal generation circuit and a second terminal of the first transistor is coupled to the pixel signal line, and
a second transistor, wherein a first terminal of the second transistor is coupled to a drain of the first transistor and a second terminal of the second transistor is electrically connected to the pixel signal line.
2. The imaging device according to claim 1 , wherein the second terminal of the first transistor and the second terminal of the second transistor are configured to receive a voltage, the voltage corresponding to the pixel signal.
3. The imaging device according to claim 1 , the comparator including:
a third transistor coupled to a power supply line.
4. The imaging device according to claim 3 , wherein a gate of the third transistor is configured to receive a bias voltage.
5. The imaging device according to claim 1 , the comparator including:
a third transistor, wherein a gate of the third transistor is coupled to the drain of the first transistor and a source of the third transistor is coupled to the pixel signal line.
6. The imaging device according to claim 5 , wherein the gate of the third transistor is coupled to a drain of the third transistor.
7. The imaging device according to claim 5 , wherein a bottom gate of the third transistor is coupled to the source of the third transistor.
8. The imaging device according to claim 5 , the comparator further comprising:
a fourth transistor, wherein a drain of the fourth transistor is coupled to the pixel signal line and a source of the fourth transistor is coupled to a drain of the second transistor.
9. The imaging device according to claim 8 , wherein a gate of the fourth transistor is configured to receive a bias voltage.
10. The imaging device according to claim 1 , wherein the first terminal of the first transistor is a bottom gate of the first transistor that is connected to the second terminal of the first transistor, and the first terminal of the second transistor is a bottom gate of the second transistor that is connected to the second terminal of the second transistor.
11. The imaging device according to claim 1 , wherein the pixel is disposed in a first substrate and the comparator is disposed in a second substrate which is bonded to the first substrate.
12. The imaging device according to claim 11 , wherein the first substrate and the second substrate are electrically connected by a through silicon via.
13. The imaging device according to claim 11 , wherein the first substrate and the second substrate are electrically connected by a direct bonding.
14. The imaging device according to claim 1 , wherein
the first terminal of the first transistor is a gate of the first transistor,
the second terminal of the first transistor is a source of the first transistor,
the first terminal of the second transistor is a gate of the second transistor, and
the second terminal of the second transistor is a source of the second transistor.
15. The imaging device according to claim 1 , further comprising
a comparator including a third transistor, wherein a first terminal of the third transistor is coupled to the pixel signal line and a second terminal of the third transistor is coupled to a power supply terminal.
16. The imaging device according to claim 15 , wherein the first terminal of the third transistor is a drain of the third transistor, and the second terminal of the third transistor is a source of the third transistor.
17. A comparator comprising:
a first input configured to receive a pixel signal;
a second input configured to receive a reference signal;
a first transistor, wherein a first terminal of the first transistor is coupled to the reference signal generation circuit and a second terminal of the first transistor is coupled to the first input; and
a second transistor, wherein a first terminal of the second transistor is coupled to a drain of the first transistor and a second terminal of the second transistor is electrically connected to the first input.
18. The comparator according to claim 17 , wherein the second terminal of the first transistor and the second terminal of the second transistor are configured to receive a voltage, the voltage corresponding to the pixel signal.
19. The comparator according to claim 17 , comprising:
a third transistor, wherein a drain of the third transistor is coupled to the first input and a source of the third transistor is coupled to the drain of the first transistor.
20. The imaging device according to claim 19 , wherein a gate of the third transistor is configured to receive a bias voltage.
21. The comparator according to claim 17 , comprising:
a third transistor coupled to a power supply line.
22. The comparator according to claim 21 , wherein the gate of the third transistor is coupled to a drain of the third transistor.
23. The comparator according to claim 21 , wherein a bottom gate of the third transistor is coupled to the source of the third transistor.
24. The comparator according to claim 21 , the comparator further comprising:
a fourth transistor, wherein a drain of the fourth transistor is coupled to the first input and a source of the fourth transistor is coupled to a drain of the second transistor.
25. The comparator according to claim 24 , wherein a gate of the fourth transistor is configured to receive a bias voltage.
26. The comparator according to claim 17 , wherein the first terminal of the first transistor is a bottom gate of the first transistor that is connected to the second terminal of the first transistor, and the first terminal of the second transistor is a bottom gate of the second transistor that is connected to the second terminal of the second transistor.
27. The comparator according to claim 17 , wherein
the first terminal of the first transistor is a gate of the first transistor,
the second terminal of the first transistor is a source of the first transistor,
the first terminal of the second transistor is a gate of the second transistor, and
the second terminal of the second transistor is a source of the second transistor.