Read retry to selectively disable on-die ECC
A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.
1. A memory device comprising:
a hardware interface to receive a first read command for an address from a host; and
on-die error checking and correction (ECC) circuitry to receive read data, process the read data internally to the memory device with the on-die ECC circuitry to generate ECC processed read data, and return the ECC processed read data from the address to the host in response to the first read command, wherein in response to detection of a detected, uncorrectable error (DUE) by the on-die ECC circuitry, the on-die ECC circuitry is also to return a DUE indication to the host in response to the first read command;
wherein the hardware interface is to receive a second read command from the host to the address subsequent to the first read command, in response to the DUE indication; and
wherein the second read command is to disable application of the on-die ECC circuitry, to trigger the memory device to return the read data from the address not processed by the on-die ECC circuitry in response to the second read command.
2. The memory device of claim 1 , wherein the second read command comprises a command having a command encoding to trigger disabling of the application of the on-die ECC circuitry.
3. The memory device of claim 1 , wherein the second read command comprises a sequence of read commands to the address without other intervening commands to trigger disabling of the application of the on-die ECC circuitry.
4. The memory device of claim 3 , further comprising a register to store the address.
5. The memory device of claim 1 , further comprising:
a mode register to store a field to indicate application of on-die ECC;
wherein the second read command comprises a read command received when the field indicates application of the on-die ECC is disabled.
6. The memory device of claim 1 , wherein to disable application of the on-die ECC circuitry comprises a bypass of the on-die ECC circuitry in response to the second read command.
7. The memory device of claim 1 , wherein the memory device comprises one of multiple memory devices coupled in parallel, and wherein after the second read command, the hardware interface is to receive a command to trigger performance of permanent fault detection (PFD) to determine which of multiple memory devices generated the DUE indication.
8. The memory device of claim 1 , wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate (DDR) standard.
9. A method for a memory device, comprising:
returning a detected, uncorrectable error (DUE) indication from on-die error checking and correction (ECC) in response to a first read command for an address;
receiving a second read command for the address in response to the DUE indication;
disabling application of the on-die ECC in response to the second read command; and
returning raw data from the address without application of the on-die ECC in response to the second read command.
10. The method of claim 9 , wherein receiving the second read command comprises decoding the command to identify the command as a read command without application of the on-die ECC.
11. The method of claim 10 , wherein identifying the command comprises identifying command encoding to trigger disabling of the application of the on-die ECC.
12. The method of claim 10 , wherein identifying the command comprises identifying the command as a second of a sequence of read commands to the address without other intervening commands.
13. The method of claim 10 , wherein identifying the command comprises identifying a read command received when a field in a mode register indicates disabling application of the on-die ECC.
14. The method of claim 9 , wherein disabling application of the on-die ECC comprises bypassing on-die ECC circuitry in response to the second read command.
15. A method for a memory controller comprising:
receiving an indication of a detected, uncorrectable error (DUE) indication from a memory device with on-die error checking and correction (ECC) in response to a first read command for an address;
sending a second read command to the memory device for the address in response to the DUE indication, the second read command to trigger disabling application of the on-die ECC; and
receiving raw data from the address without application of the on-die ECC in response to the second read command.
16. The method of claim 15 , wherein sending the second read command comprises sending a command having a command encoding to trigger disabling of the application of the on-die ECC.
17. The method of claim 15 , wherein sending the second read command comprises sending the second read command as a second of a sequence of read commands to the address without other intervening commands.
18. The method of claim 15 , wherein sending the second read command comprises:
writing a field of a mode register of the memory device to indicate application of the on-die ECC is disabled; and
sending the second read command when the field indicates the application of the on-die ECC is disabled.
19. The method of claim 15 , wherein triggering disabling of the application of the on-die ECC comprises triggering a bypass of on-die ECC circuitry in response to the second read command.
20. The method of claim 15 , wherein the memory device comprises one of multiple memory devices coupled in parallel, and further comprising performing permanent fault detection (PFD) to determine which of the multiple memory devices generated the DUE indication.