IP Library Granted Patent US 11,966,303
Granted Patent B2
US 11,966,303 · App. 17/877,779 · Granted Apr 23, 2024

Memory system failure detection and self recovery of memory dice

Inventors: Robert Mason (Boise, ID); Scott A. Stoller (Boise, ID); Pitamber Shukla (Boise, ID); Kenneth W. Marr (Boise, ID); Chi Ming Chu (Boise, ID); Hossein Afkhami (Berkeley, CA)
Assignee: MICRON TECHNOLOGY, INC.
G06F11/1471G06F9/30098G06F11/1469
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Quick Facts
Patent No.
US 11,966,303
App. No.
17/877,779
Granted
Apr 23, 2024
Kind
B2
Abstract

Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

Claims (69)

1. A method of error recovery, the method comprising:

detecting a failure of a memory device;

retrieving a set of register values from the memory device;

storing the set of register values from the memory device;

issuing a reset command to the memory device, wherein the reset command includes generating a re-initialized set of register values;

comparing the set of register values with the re-initialized set of register values; and

triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

2. The method of claim 1 , wherein detecting the failure comprises detecting an indication of a retirement of one or more dice of the memory device.

3. The method of claim 1 , wherein the reset command includes a power cycling, and wherein the re-initialized set of register values correspond to a default value stored in a non-volatile storage location.

4. The method of claim 1 further comprising:

identifying, based on the comparison of the set of register values with the re-initialized set of register values, that the set of register values represents an unexpected state;

recovering, in response to identifying the unexpected state, from the unexpected state using the re-initialized set of register values; and

determining, in response to recovering from the unexpected state, a status of the memory device.

5. The method of claim 1 , wherein detecting the failure of the memory device comprises identifying a number of grown bad blocks over a time interval satisfies a threshold rate of grown bad blocks.

6. The method of claim 1 , wherein detecting the failure of the memory device comprises:

computing a rate of failures of the memory device;

comparing the rate of failures with an expected failure rate of the memory device, wherein the expected failure rate is a statistical estimate of manufacturing deviation; and

determining a failure state when the rate of failures is greater than the expected failure rate.

7. The method of claim 1 , wherein triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values comprises:

computing a difference of the set of register values and the re-initialized set of register values;

determining that the difference satisfies a threshold; and

in response to determining that the difference satisfies a threshold, triggering a self-recovery attempt.

8. The method of claim 7 , further comprising:

determining that the difference does not satisfy a threshold; and

in response to determining that the difference does not satisfy a threshold, resuming normal error handling.

9. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

detect a failure of a memory device;

retrieve a set of trim values from the memory device;

store the set of trim values in a non-volatile memory location;

issue a reset command to the memory device, wherein the reset command includes generating a re-initialized set of trim values;

compare the set of trim values with the re-initialized set of trim values; and

trigger a self-recovery attempt using the comparison of the set of trim values with the re-initialized set of trim values.

10. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions that cause the processing device to detect the failure comprise instructions that, when executed by a processing device, cause the processing device to detect an indication of a retirement of one or more dice of the memory device.

11. The non-transitory computer-readable storage medium of claim 9 , wherein the reset command includes a power cycling, and wherein the re-initialized set of trim values are a set of default values stored in a non-volatile storage location.

12. The non-transitory computer-readable storage medium of claim 9 , the instructions further causing the processing device to:

identify, using the comparison of the set of trim values with the re-initialized set of trim values, that the set of trim values represents an unexpected state;

recover from the unexpected state using the re-initialized set of trim values; and

determine, in response to recovering from the unexpected state, a status of the memory device.

13. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions that cause the processing device to detect the failure of the memory device comprise instructions that, when executed by a processing device, cause the processing device to identify a number of grown bad blocks over a time interval satisfies a threshold rate of grown bad blocks.

14. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions that cause the processing device to detect the failure of the memory device comprise instructions that, when executed by a processing device, cause the processing device to:

compute a rate of failures of the memory device;

compare the rate of failures with an expected failure rate of the memory device, wherein the expected failure rate is a statistical estimate of manufacturing deviation; and

determine a failure state when the rate of failures is greater than the expected failure rate.

15. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions that cause the processing device to trigger a self-recovery attempt using the comparison of the set of trim values with the re-initialized set of trim values comprise instructions that, when executed by a processing device, cause the processing device to:

compute a difference of the set of trim values and the re-initialized set of trim values;

determine that the difference satisfies a threshold; and

in response to determining that the difference satisfies a threshold, trigger a self-recovery attempt.

16. A system comprising:

a plurality of memory devices; and

a processing device, operatively coupled with the plurality of memory devices, to:

detect a failure of a memory device;

retrieve a set of trim values from the memory device;

store the set of trim values from the memory device;

issue a reset command to the memory device, wherein the reset command includes generating a re-initialized set of trim values;

compare the set of trim values with the re-initialized set of trim values; and

trigger a self-recovery attempt using the comparison of the set of trim values with the re-initialized set of trim values, wherein triggering the self-recovery attempt comprises:

computing a difference of the set of register values and the re-initialized set of register values;

determining that the difference satisfies a threshold; and

in response to determining that the difference satisfies a threshold, triggering a self-recovery attempt.

17. The system of claim 16 , the processing device, operatively coupled with the plurality of memory devices, further to detect an indication of a retirement of one or more dice of the memory device.

18. The system of claim 16 , wherein the reset command includes a power cycling, and wherein the re-initialized set of trim values correspond to a set of default values.

19. The system of claim 16 , the processing device, operatively coupled with the plurality of memory devices, further to:

identify, based on the comparison of the set of trim values with the re-initialized set of trim values, that the set of trim values represents an unexpected state;

recover from the unexpected state using the re-initialized set of trim values; and

determine, in response to recovering from the unexpected state, a status of the memory device.

20. The system of claim 16 , the processing device, operatively coupled with the plurality of memory devices, further to:

compute a rate of failures of the memory device;

compare the rate of failures with an expected failure rate of the memory device, wherein the expected failure rate is a statistical estimate of manufacturing deviation; and

determine a failure state when the rate of failures is greater than the expected failure rate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2022
From: MASON, ROBERT; STOLLER, SCOTT A.; SHUKLA, PITAMBER; MARR, KENNETH W.; CHU, CHI MING; AFKHAMI, HOSSEIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 060677/0668 →
Continuity (2)
Provisional Application 63348297 · Jun 2, 2022
Related Publication 20230393955A1 · Dec 7, 2023
Cited By (2)
US 12,671,671 US 12,724,647