IP Library › Granted Patent US 11,967,060
Granted Patent B2
US 11,967,060 · App. 17/405,014 · Granted Apr 23, 2024

Wafer level spatial signature grouping using transfer learning

Inventors: Narayani Narasimhan (New Delhi, IN); Alán Dávila (Pflugerville, TX); P. Jithendra Kumar Reddy (Hyderabad, IN); Ski Sim (Singapore, SG); Osamu Yamamoto (Kanagawa, JP)
Assignee: KLA CORPORATION
G06T7/0004G06T2207/20081G06T2207/20084G06T2207/30148
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Quick Facts
Patent No.
US 11,967,060
App. No.
17/405,014
Filed
Aug 17, 2021
Granted
Apr 23, 2024
Kind
B2
Art Unit
2877
USPC
382/149
Abstract

A wafer map is classified using the machine learning based model and a signature on the wafer map. The machine learning based model uses transfer learning. The machine learning based model can be trained using images from various sources that are extracted and augmented and their features extracted. These extracted features can be classified into defects that occur during semiconductor manufacturing.

Claims (47)

1. A method comprising:

receiving, a wafer map at a processor, wherein the wafer map is for a surface of an entire wafer, wherein the processor is configured to run a machine learning based model for classifying the wafer map;

classifying the wafer map using the machine learning based model and a signature on the wafer map, wherein the machine learning based model uses transfer learning, and wherein a confidence matrix is used to control purity of signature classes in the machine learning based model;

determining a confidence level for the classifying, wherein the confidence level is based on criticality of a defect in the signature; and

determining if the signature is outside of the confidence level.

2. The method of claim 1 , further comprising sending an alert if the signature is outside of the confidence level.

3. The method of claim 1 , further comprising:

receiving a plurality of sample wafer maps at the processor;

classifying the sample wafer maps based on a root cause of a defect using the processor; and

generating a library of sample signatures from the sample wafer maps using the processor.

4. The method of claim 3 , further comprising:

extracting images from a plurality of defect maps, bin sort maps, and/or metrology maps using the processor; and

augmenting the images using the processor.

5. The method of claim 4 , further comprising training the machine learning based model using extracted features from the images.

6. The method of claim 1 , further comprising grouping the wafer map with wafer maps having a same classification.

7. A system comprising:

a semiconductor wafer inspection system; and

a processor in electronic communication with the semiconductor wafer inspection system,

wherein the processor is configured to:

receive a wafer map, wherein the wafer map is for a surface of an entire wafer, wherein the processor is configured to run a machine learning based model for classifying the wafer map;

classify the wafer map using the machine learning based model and a signature on the wafer map, wherein the machine learning based model uses transfer learning, and wherein a confidence matrix is used to control purity of signature classes in the machine learning based model;

determine a confidence level for the classifying, wherein the confidence level is based on criticality of a defect in the signature; and

determine if the signature is outside of the confidence level.

8. The system of claim 7 , wherein the semiconductor wafer inspection system includes a light source or an electron beam source.

9. The system of claim 7 , wherein the semiconductor wafer inspection system generates the wafer map.

10. The system of claim 7 , wherein the processor is further configured to send an alert if the signature is outside of the confidence level.

11. The system of claim 7 , wherein the processor is further configured to:

receive a plurality of sample wafer maps;

classify the sample wafer maps based on a root cause of a defect; and

generate a library of sample signatures from the sample wafer maps.

12. The system of claim 11 , wherein the processor is further configured to:

extract images from a plurality of defect maps, bin sort maps, and/or metrology maps; and

augment the images.

13. The system of claim 12 , wherein the processor is further configured to train the machine learning based model using extracted features from the images.

14. The system of claim 7 , wherein the processor is further configured to group the wafer map with wafer maps having a same classification.

15. A non-transitory computer-readable storage medium, comprising one or more programs for executing the following steps on one or more computing devices:

classifying a wafer map using a machine learning based model and a signature on the wafer map, wherein the machine learning based model uses transfer learning, wherein the wafer map is for a surface of an entire wafer, and wherein a confidence matrix is used to control purity of signature classes in the machine learning based model;

determining a confidence level for the classifying, wherein the confidence level is based on criticality of a defect in the signature; and

determining if the signature is outside of the confidence level.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the steps further include:

receiving a plurality of sample wafer maps;

classifying the sample wafer maps based on a root cause of a defect; and

generating a library of sample signatures from the sample wafer maps.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the steps further include:

extracting images from a plurality of defect maps, bin sort maps, and/or metrology maps; and

augmenting the images.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the steps further include training the machine learning based model using extracted features from the images.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2021
From: NARASIMHAN, NARAYANI; DAVILA, ALAN; REDDY, P. JITHENDRA KUMAR; SIM, SKI; YAMAMOTO, OSAMU
To: KLA CORPORATION
Reel/Frame 058096/0186 →
Priority Claims (1)
IN 202041036573 · Aug 25, 2020 · national
Continuity (2)
Provisional Application 63089036 · Oct 8, 2020
Related Publication 20220067911A1 · Mar 3, 2022
Cited By (1)
US 12,657,689