Fan-out package having a main die and a dummy die
A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
1. A semiconductor structure, comprising:
a functional die on a first polymer layer, wherein the functional die comprises a first insulating layer over a first substrate;
a dummy die on the first polymer layer, wherein the dummy die comprises a second insulating layer overlying a second substrate, wherein the dummy die is free of active devices;
a molding compound along sidewalls of the functional die and the dummy die; and
a redistribution structure over the functional die, the dummy die, and the molding compound, the redistribution structure comprising a first conductive line electrically coupled to the functional die, wherein the redistribution structure comprises a first external contact on a side opposite the functional die.
2. The structure of claim 1 , further comprising one or more through vias on the first substrate, wherein the one or more through vias are connected to corresponding conductive elements of the redistribution structure.
3. The structure of claim 2 , wherein the one or more through vias include a first through via and a second through via, wherein the functional die and the dummy die are interposed between the first through via and the second through via.
4. The structure of claim 2 , further comprising an external contact, wherein the external contact extends through the first polymer layer to the first through via.
5. The structure of claim 1 , wherein the functional die is a first functional die of one or more functional dies, wherein the dummy die is a first dummy die of one or more dummy dies, wherein an area of the semiconductor structure in a plan view is a first area, an area of the semiconductor structure covered by the one or more functional dies and the one or more dummy dies in the plan view of the semiconductor structure is a second area, and wherein a ratio of the first area to the second area is 2.5 or less.
6. The structure of claim 5 , wherein the first functional die is interposed between the first dummy die and a second dummy die of the one or more dummy dies.
7. The structure of claim 1 , wherein the dummy die comprises a plurality of conductive elements in the second insulating layer.
8. The structure of claim 7 , wherein the plurality of conductive elements contacts the redistribution structure.
9. The structure of claim 7 , wherein the plurality of conductive elements are coupled to ground.
10. A semiconductor structure, comprising:
a functional die on a first surface, the functional die comprising a first substrate and a first insulating layer on the first substrate;
a first dummy die on the first surface, the first dummy die comprising a second substrate and a second insulating layer on the second substrate, wherein the first insulating layer and the second insulating layer face a same direction relative to the first surface;
a molding material on the first surface, the molding material extending between the first dummy die and the functional die, wherein the molding material completely covers sidewalls of the second insulating layer; and
a redistribution structure over the functional die and the molding material, wherein the redistribution structure comprises an external contact electrically coupled to the functional die, wherein the molding material extends between the first dummy die and the redistribution structure.
11. The structure of claim 10 , wherein the first surface is a surface of a polymer layer.
12. The structure of claim 11 , wherein the functional die and the first dummy die are attached to the polymer layer by an adhesive.
13. The structure of claim 11 , further comprising a through via in the molding material, wherein the through via comprises a seed layer on the polymer layer and a metal feature on the seed layer, wherein the seed layer is interposed between the metal feature and the polymer layer.
14. The structure of claim 10 , wherein a thickness of the first dummy die is less than a thickness of the functional die.
15. The structure of claim 14 , wherein a thickness of the first dummy die is less than a thickness of the molding material.
16. A semiconductor structure, comprising:
a functional die on a first surface of a first structure, the functional die comprising a first substrate and a first insulating layer on the first substrate, wherein the first substrate is interposed between the first structure and the first insulating layer;
a first dummy die on the first surface of the first structure laterally spaced apart from the functional die, the first dummy die comprising a second substrate and a second insulating layer on the second substrate, wherein the second substrate is interposed between the first structure and the second insulating layer;
a molding material on the first surface, the molding material extending between the first dummy die and the functional die, wherein the molding material completely covers sidewalls of the second insulating layer; and
a redistribution structure on the functional die, the first dummy die, and the molding material, wherein the redistribution structure comprises an external contact electrically coupled to the electrical contact of the functional die, wherein the redistribution structure contacts the first insulating layer and the second insulating layer.
17. The structure of claim 16 , wherein a thickness of the functional die is a same thickness as a thickness of the first dummy die.
18. The structure of claim 16 , wherein the first substrate and the second substrate have a same material composition.
19. The structure of claim 16 , wherein the first dummy die further comprises a plurality of conductive contacts in the second insulating layer.
20. The structure of claim 16 , further comprising a third insulating layer, wherein second substrate is interposed between the third insulating layer and the second insulating layer.