Aging mitigation
Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.
1. A system, comprising:
a multiplexer having a first input, a second input, a select input, and an output, wherein the first input of the multiplexer is configured to receive a clock signal;
a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer; and
a controller coupled to the second input of the multiplexer and the select input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to:
receive a mode indicator signal at the indicator input;
if the mode indicator signal has a first logic value, instruct the multiplexer to select the first input of the multiplexer; and
if the mode indicator signal has a second logic value, instruct the multiplexer to select the second input of the multiplexer, output a control signal to the second input of the multiplexer, and alternately set the control signal high and low over multiple consecutive idle periods.
2. The system of claim 1 , wherein the signal path comprises a delay circuit.
3. The system of claim 2 , wherein the delay circuit comprises delay buffers coupled in series.
4. The system of claim 1 , wherein the first logic value indicates the system is in an active mode, and the second logic value indicates the system is in an idle mode.
5. The system of claim 1 , wherein the consecutive idle periods include odd idle periods and even idle periods, and the controller is configured to:
set the control signal low during each of the odd idle periods; and
set the control signal high during each of the even idle periods.
6. The system of claim 1 , wherein the consecutive idle periods include odd idle periods and even idle periods, and the controller is configured to:
set the control signal high during each of the odd idle periods; and
set the control signal low during each of the even idle periods.
7. The system of claim 1 , further comprising:
a pad; and
a receiver having an input and an output, wherein the input of the receiver is coupled to the pad, and the output of the receiver is coupled to the first input of the multiplexer.
8. The system of claim 1 , further comprising:
a pad; and
a driver having an input and an output, wherein the input of the driver is coupled to the output of the signal path, and the output of the driver is coupled to the pad.
9. The system of claim 1 , further comprising:
a latching circuit having a signal input, a clock input, and an output, wherein the clock input is coupled to the output of the signal path.
10. The system of claim 1 , further comprising:
a driver; and
a clock gating circuit coupled between the output of the signal path and an input of the driver, wherein the controller is configured to un-gate the clock gating circuit if the mode indicator has the first logic value, and gate the clock gating circuit if the mode indicator has the second logic value.
11. The system of claim 10 , wherein the first logic value indicates the system is in an active mode, and the second logic value indicates the system is in an idle mode.
12. A system, comprising:
a multiplexer having a first input, a second input, a select input, and an output, wherein the first input of the multiplexer is configured to receive a clock signal;
a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer; and
a controller coupled to the second input of the multiplexer and the select input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to:
receive a mode indicator signal at the indicator input;
if the mode indicator signal has a first logic value, instruct the multiplexer to select the first input of the multiplexer; and
if the mode indicator signal has a second logic value, instruct the multiplexer to select the second input of the multiplexer, output a control signal to the second input of the multiplexer, set the control signal high for k of N consecutive idle periods, and set the control signal low for N-k of the N consecutive idle periods, wherein k is an integer equal to or greater than one, and N is an integer greater than k.
13. The system of claim 12 , wherein the controller is configured to store a sequence of bits in a register, each of the bits in the sequence of bits corresponding to a respective one of the N consecutive idle periods in an idle mode, and wherein, for each one of the N consecutive idle periods, the controller is configured to:
set the control signal high during the idle period if the corresponding bit in the sequence of bits has a first bit value; and
set the control signal low during the idle period if the corresponding bit in the sequence of bits has a second bit value.
14. The system of claim 12 , wherein the controller comprises:
a circular shift register having an input and an output, wherein the output of the circular shifter register is coupled to the second input of the multiplexer; and
a control circuit having an input, a first output, and a second output, wherein the input of the control circuit is coupled to the indicator input, the first output of the control circuit is coupled to the select input of the multiplexer, and the second output of the control circuit is coupled to the input of the circular shift register.
15. The system of claim 14 , wherein:
the circular shifter register is configured to store bits, each of the bits corresponding to a respective one of the N consecutive idle periods, and to output one of the bits at a time at the output of the circular shift register;
the control circuit is configured to:
receive the mode indicator signal via the input of the control circuit;
if the mode indicator signal has the first logic value, instruct the multiplexer to select the first input; and
if the mode indicator signal has the second logic value, instruct the multiplexer to select the second input via the first output, and instruct the circular shift register to shift the bits in the circular shift register via the second output.
16. The system of claim 12 , further comprising:
a driver; and
a clock gating circuit coupled between the output of the signal path and an input of the driver, wherein the controller is configured to un-gate the clock gating circuit if the mode indicator has the first logic value, and gate the clock gating circuit if the mode indicator has the second logic value.
17. The system of claim 16 , wherein the first logic value indicates the system is in an active mode, and the second logic value indicates the system is in an idle mode.
18. A system, comprising:
a latching circuit having a signal input, a clock input, a set input, a reset input, and an output, wherein the latching circuit is configured to latch a logic value at the signal input on an edge of a clock signal input to the clock input when the set input and the reset input are de-asserted, and output the latched logic value at the output of the latching circuit;
a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the latching circuit; and
a controller coupled to the set input and the reset input of the latching circuit, wherein the controller has an indicator input, and the controller is configured to:
receive a mode indicator signal at the indicator input;
if the mode indicator signal has a first logic value, de-assert the set input and the reset input; and
if the mode indicator signal has a second logic value, alternately assert the set input and the reset input over multiple consecutive idle periods.
19. The system of claim 18 , wherein the first logic value indicates the system is in an active mode, and the second logic value indicates the system is in an idle mode.
20. The system of claim 18 , wherein the signal input of the latching circuit is configured to receive a data signal, a command signal, or an address signal.
21. The system of claim 18 , wherein the signal path comprises a delay circuit.
22. The system of claim 21 , wherein the delay circuit comprises delay buffers coupled in series.
23. The system of claim 18 , wherein the consecutive idle periods include odd idle periods and even idle periods, and the controller is configured to:
assert the set input during each of the odd idle periods; and
assert the reset input during each of the even idle periods.
24. The system of claim 18 , wherein the consecutive idle periods include odd idle periods and even idle periods, and the controller is configured to:
assert the reset input during each of the odd idle periods; and
assert the set input during each of the even idle periods.
25. The system of claim 18 , further comprising:
a pad; and
a receiver having an input and an output, wherein the input of the receiver is coupled to the pad, and the output of the receiver is coupled to the signal input of the latching circuit.
26. The system of claim 18 , further comprising:
a pad; and
a driver having an input and an output, wherein the input of the driver is coupled to the output of the signal path, and the output of the driver is coupled to the pad.
27. The system of claim 18 , wherein the latching circuit is configured to output a logic one at the output of the latching circuit when the controller asserts the set input, and output a logic zero at the output of the latching circuit when the controller asserts the reset input.
28. A system, comprising:
a latching circuit having a signal input, a clock input, a set input, a reset input, and an output, wherein the latching circuit is configured to latch a logic value at the signal input on an edge of a clock signal input to the clock input when the set input and the reset input are de-asserted, and output the latched logic value at the output of the latching circuit;
a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the latching circuit; and
a controller coupled to the set input and the reset input of the latching circuit, wherein the controller has an indicator input, and the controller is configured to:
receive a mode indicator signal at the indicator input;
if the mode indicator signal has a first logic value, de-assert the set input and the reset input; and
if the mode indicator signal has a second logic value, assert the set input for k of N consecutive idle periods, and assert the reset input for N-k of the N consecutive idle periods, wherein k is an integer equal to or greater than one, and N is an integer greater than k.
29. The system of claim 28 , wherein the controller is configured to store a sequence of bits in a register, each of the bits in the sequence of bits corresponding to a respective one of the N consecutive idle periods in an idle mode, and wherein, for each one of the N consecutive idle periods, the controller is configured to:
assert the set input during the idle period if the corresponding bit in the sequence of bits has a first bit value; and
assert the reset input during the idle period if the corresponding bit in the sequence of bits has a second bit value.
30. The system of claim 28 , wherein the latching circuit is configured to output a logic one at the output of the latching circuit when the controller asserts the set input, and output a logic zero at the output of the latching circuit when the controller asserts the reset input.
31. A method for aging control in a system including a multiplexer and a signal path coupled to an output of the multiplexer, comprising:
in an active mode,
instructing the multiplexer to select a first input of the multiplexer; and
inputting a clock signal to the first input of the multiplexer; and
in an idle mode,
instructing the multiplexer to select a second input of the multiplexer;
inputting a control signal to the second input of the multiplexer; and
alternately setting the control signal high and low over multiple consecutive idle periods.
32. The method of claim 31 , further comprising inputting a data signal, a clock signal, a control signal, or an address signal to the first input of the multiplexer in the active mode.
33. The method of claim 31 , wherein the signal path comprises a delay circuit.
34. The method of claim 33 , wherein the delay circuit comprises delay buffers coupled in series.
35. The method of claim 31 , wherein the consecutive idle periods include odd idle periods and even idle periods, and alternately setting the control signal high and low comprises:
setting the control signal low during each of the odd idle periods; and
setting the control signal high during each of the even idle periods.
36. The method of claim 31 , wherein the consecutive idle periods include odd idle periods and even idle periods, and alternately setting the control signal high and low comprises:
setting the control signal high during each of the odd idle periods; and
setting the control signal low during each of the even idle periods.
37. A method for aging control, in a system including a multiplexer and a signal path coupled to an output of the multiplexer, comprising:
in an active mode,
instructing the multiplexer to select a first input of the multiplexer; and
inputting a clock signal to the first input of the multiplexer; and
in an idle mode,
instructing the multiplexer to select a second input of the multiplexer;
inputting a control signal to the second input of the multiplexer;
setting the control signal high for k of N consecutive idle periods; and
setting the control signal low for N-k of the N consecutive idle periods;
wherein k is an integer equal to or greater than one, and N is an integer greater than k.
38. The method of claim 37 , further comprising storing a sequence of bits in a register, each of the bits in the sequence of bits corresponding to a respective one of the N consecutive idle periods in the idle mode, and wherein:
setting the control signal high for k of N consecutive idle periods comprises, for each one of the N consecutive idle periods, setting the control signal high during the idle period if the corresponding bit in the sequence of bits has a first bit value; and
setting the control signal low for N-k of the N consecutive idle periods comprises, for each one of the N consecutive idle periods, setting the control signal low during the idle period if the corresponding bit in the sequence of bits has a second bit value.
39. A system, comprising:
a multiplexer having a first input, a second input, a select input, and an output;
a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer;
a latching circuit having a signal input, a clock input, and an output, wherein the signal input is coupled to the output of the signal path, the clock input of the latching circuit is configured to receive a clock signal, and the latching circuit is configured to latch a logic value at the signal input on an edge of the clock signal, and output the latched logic value at the output of the latching circuit; and
a controller coupled to the second input of the multiplexer and the select input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to:
receive a mode indicator signal at the indicator input;
if the mode indicator signal has a first logic value, instruct the multiplexer to select the first input of the multiplexer; and
if the mode indicator signal has a second logic value, instruct the multiplexer to select the second input of the multiplexer, output a control signal to the second input of the multiplexer, and alternately set the control signal high and low over multiple consecutive idle periods.
40. The system of claim 39 , wherein the first input of the multiplexer is configured to receive a data signal, a command signal, or an address signal.
41. A system, comprising:
a multiplexer having a first input, a second input, a select input, and an output;
a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer;
a latching circuit having a signal input, a clock input, and an output, wherein the signal input is coupled to the output of the signal path, the clock input of the latching circuit is configured to receive a clock signal, and the latching circuit is configured to latch a logic value at the signal input on an edge of the clock signal, and output the latched logic value at the output of the latching circuit; and
a controller coupled to the second input of the multiplexer and the select input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to:
receive a mode indicator signal at the indicator input;
if the mode indicator signal has a first logic value, instruct the multiplexer to select the first input of the multiplexer; and
if the mode indicator signal has a second logic value, instruct the multiplexer to select the second input of the multiplexer, output a control signal to the second input of the multiplexer, set the control signal high for k of N consecutive idle periods, and set the control signal low for N−k of the N consecutive idle periods, wherein k is an integer equal to or greater than one, and N is an integer greater than k.
42. The system of claim 41 , wherein the first input of the multiplexer is configured to receive a data signal, a command signal, or an address signal.