Semiconductor structure and manufacturing method thereof
A semiconductor structure and a manufacturing method thereof are provided. The method includes: providing a substrate; forming, on the substrate, a first mask layer having a plurality of strip-shaped first patterns arranged in parallel; forming, on the first mask layer, a second mask layer having a plurality of strip-shaped second patterns arranged in parallel; forming, on the second mask layer, a third mask layer having a plurality of strip-shaped third patterns arranged in parallel, the second patterns overlap with the third patterns, and the second patterns and the third patterns are configured to sever the first patterns at predetermined positions; and performing layer-by-layer etching, using the first mask layer, the second mask layer, and the third mask layer as masks to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas.
1. A semiconductor structure manufacturing method, comprising:
providing a substrate;
forming a first mask layer on the substrate, the first mask layer having a plurality of strip-shaped first patterns arranged in parallel and configured to form a plurality of strip-shaped continuous active areas arranged in parallel in the substrate;
forming a second mask layer on the first mask layer, the second mask layer having a plurality of strip-shaped second patterns arranged in parallel;
forming a third mask layer on the second mask layer, the third mask layer having a plurality of strip-shaped third patterns arranged in parallel and overlapping the second patterns, wherein the second patterns and the third patterns are configured to sever the first patterns at predetermined positions;
performing layer-by-layer etching, using the first mask layer, the second mask layer, and the third mask layer as masks, to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas, wherein the substrate comprises an array area, and the first patterns, the second patterns, and the third patterns are all formed at least in the array area; and
forming a fourth mask layer on the third mask layer, the fourth mask layer having sixth patterns covering at least a portion of the second patterns and at least a portion of the third patterns at an edge portion of the array area, wherein the fourth mask layer is not extended to a portion of the array area other than the edge portion.
2. The semiconductor structure manufacturing method of claim 1 , wherein the sixth patterns further cover a sub-active area at an end of the continuous active area at the edge of the array area, the sub-active area having a length less than that of the discrete active area, and wherein performing layer-by-layer etching to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas comprises:
transferring, using the first mask layer, the second mask layer, the third mask layer, and the fourth mask layer as masks, the first patterns, the second patterns, the third patterns, and the sixth patterns to the substrate to form the array of the discrete active areas, wherein there is no sub-active area at the edge of the array area.
3. The semiconductor structure manufacturing method of claim 1 , wherein the first patterns are formed by using a self-aligned double patterning technology.
4. The semiconductor structure manufacturing method of claim 1 , wherein the array area is a storage array area of a dynamic random-access memory.
5. The semiconductor structure manufacturing method of claim 1 , wherein the first mask layer, the second mask layer, and the third mask layer are made of at least one of silicon dioxide, silicon nitride, silicon oxynitride, polycrystalline silicon, monocrystalline silicon, and carbon.
6. The semiconductor structure manufacturing method of claim 1 , wherein forming a second mask layer on the first mask layer comprises:
forming a first sacrificial layer on the first mask layer, the first sacrificial layer having a plurality of strip-shaped fourth patterns arranged in parallel;
forming a mask material on a sidewall of the fourth patterns; and
removing the first sacrificial layer while retaining the mask material on the sidewall of the fourth patterns to form the second mask layer.
7. The semiconductor structure manufacturing method of claim 6 , wherein forming a third mask layer on the second mask layer comprises:
forming a second sacrificial layer on the second mask layer, the second mask layer having a plurality of strip-shaped fifth patterns arranged in parallel;
forming the mask material on a sidewall of the fifth patterns; and
removing the second sacrificial layer while retaining the mask material on the sidewall of the fifth patterns to form the third mask layer.
8. The semiconductor structure manufacturing method of claim 7 , wherein an angle between the second patterns and the first patterns is in a range of 65 degrees to 75 degrees.
9. The semiconductor structure manufacturing method of claim 8 , wherein an angle between the second patterns and the third patterns is in a range of 45 degrees to 55 degrees.
10. The semiconductor structure manufacturing method of claim 9 , wherein a pitch of the fourth patterns is 4 to 5 times of a pitch of the first patterns, and a pitch of the fifth patterns is 3 to 4 times of the pitch of the first patterns.
11. The semiconductor structure manufacturing method of claim 8 , wherein an angle between the second patterns and the third patterns is 90 degrees.
12. The semiconductor structure manufacturing method of claim 11 , wherein a pitch of the fourth patterns is 4 to 5 times of a pitch of the first patterns, and a pitch of the fifth patterns is 4 to 5 times of the pitch of the first patterns.