Package substrate having porous dielectric layer

1. A multilayer package substrate, comprising:

a plurality of dielectric layers including a top dielectric layer on a top side and a bottom dielectric layer on a bottom side;

a top patterned metal layer on the top dielectric layer and a bottom patterned metal layer on the bottom dielectric layer,

wherein at least one of the top dielectric layer and the bottom dielectric layer comprises a porous dielectric layer having a plurality of pores including an average porosity of at least 5% averaged over its thickness.

2. The multilayer package substrate of claim 1 , wherein the thickness of the porous dielectric layer is between 20 μm and 50 μm.

3. The multilayer package substrate of claim 1 , wherein the porous dielectric layer comprises an epoxy material.

4. The multilayer package substrate of claim 1 , wherein the plurality of pores include a range of nanopore sizes including a size ratio from largest to smallest of at least 2.

5. The multilayer package substrate of claim 1 , further comprising a bottom polymer layer and a core layer between the porous dielectric layer and the bottom polymer layer.

6. A semiconductor package, comprising:

a multilayer package substrate, comprising:

a core layer;

a top patterned metal layer on a top side of the core layer and a bottom patterned metal layer on a bottom side of the core layer;

a plurality of dielectric layers including a top dielectric layer on the top patterned metal layer and a bottom dielectric layer on the bottom patterned metal layer;

wherein at least one of the top dielectric layer and the bottom dielectric layer comprise a porous dielectric layer including a plurality of pores and having an average porosity of at least 5% averaged over its thickness, and

an integrated circuit (IC) die comprising a substrate including a top side semiconductor surface including circuitry having a plurality of bond pads electrically connected to nodes in the circuitry,

wherein the IC die is mounted on the multilayer package substrate or is embedded therein, and

wherein the plurality of bond pads are electrically connected to the multilayer package substrate.

7. The semiconductor package of claim 6 , wherein the IC die is flipchip mounted on the top patterned metal layer.

8. The semiconductor package of claim 6 , wherein the IC die is embedded within the multilayer package substrate.

9. The semiconductor package of claim 6 , wherein the porous dielectric layer comprises an epoxy material and wherein the thickness of the porous dielectric layer is between 20 μm and 50 μm.

10. The semiconductor package of claim 6 , wherein the plurality of pores include a range of nanopore sizes including a size ratio from largest to smallest of at least 2.

11. The semiconductor package of claim 6 , further comprising the bottom dielectric layer being a porous layer including a plurality of pores and having an average porosity of at least 5% averaged over its thickness.

12. The semiconductor package of claim 6 , wherein the IC die is embedded in the multilayer package substrate;

wherein the patterned top metal layer includes at least one antenna and the patterned bottom metal layer includes a plurality of contact pads including a first contact pad, and a plurality of filled vias;

the plurality of bond pads electrically coupled by a via-comprising die connection including at least one of the pluralities of filled vias for connecting to at least one of the patterned top metal layer and the patterned bottom metal layer, and

a plurality of metal pillars including a first metal pillar electrically coupled between the first contact pad and the antenna, and

wherein at least a first of the plurality of filled vias is electrically coupled to the first metal pillar for providing a first transmission line from the first contact pad to the antenna.

13. The semiconductor package of claim 6 , wherein the semiconductor package comprises a flipchip Ball grid array (FCBGA).