Semiconductor device and method forming the same
A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.
1. A semiconductor device, comprising:
a first metal layer,
a second metal layer, wherein from a top view, each of the first metal layer and the second metal layer has round corners; and
an inter-metal dielectric layer disposed between the first metal layer and the second metal layer, wherein the inter-metal dielectric layer comprises:
a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0;
a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and
a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0, wherein a thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.
2. The semiconductor device of claim 1 , wherein the round corners have a radius of curvature between 0.01 μm and 0.2 μm.
3. The semiconductor device of claim 1 , wherein an absolute value of the stress of the third dielectric layer is greater than an absolute value of the stress of the first dielectric layer.
4. The semiconductor device of claim 1 , further comprising a via penetrating through the inter-metal dielectric layer and electrically coupling the first metal layer and the second metal layer to form an interconnect structure.
5. The semiconductor device of claim 4 , further comprising a capacitor structure, wherein the interconnect structure and the capacitor structure have a lateral spacing between 8 μm and 30 μm.
6. The semiconductor device of claim 5 , wherein the capacitor structure further comprises:
a lower electrode; and
an upper electrode, wherein the upper electrode and the lower electrode have a vertical spacing, wherein the lateral spacing is greater than or equal to the vertical spacing.
7. The semiconductor device of claim 6 , wherein one or more of the inter-metal dielectric layer is disposed between the upper electrode and the lower electrode.
8. The semiconductor device of claim 1 , wherein the first dielectric layer and the second dielectric layer conformally cover the first metal layer, and the third dielectric layer has a planar top surface.
9. The semiconductor device of claim 1 , wherein the inter-metal dielectric layer further comprises one or more dielectric layers disposed on the third dielectric layer.
10. The semiconductor device of claim 1 , further comprising a first protection layer covering the second metal layer and a second protection layer disposed on the first protection layer, wherein a material of the first protection layer is different from a material of the second protection layer.
11. The semiconductor device of claim 1 , further comprising an inter-layer dielectric layer disposed under the first metal layer.
12. A method forming a semiconductor device, comprising:
forming a first metal layer on an inter-layer dielectric layer;
forming an inter-metal dielectric layer on the first metal layer, wherein steps of forming the inter-metal dielectric layer comprise:
conformally depositing a first dielectric layer on the first metal layer using a first deposition method, wherein the first dielectric layer has a stress value less than 0;
conformally depositing a second dielectric layer on the first dielectric layer using a second deposition method different from the first deposition method, wherein the second dielectric layer has a stress value greater than 0; and
depositing a third dielectric layer on the second dielectric layer using the first deposition method; and
forming a second metal layer on the inter-metal dielectric layer, wherein from a top view, the first metal layer and the second metal layer are formed with round corners.
13. The method of claim 12 , wherein the first deposition method comprises plasma-enhanced chemical vapor deposition, and the second deposition method comprises sub-atmospheric chemical vapor deposition.
14. The method of claim 12 , further comprising planarizing a top surface of the third dielectric layer before forming the second metal layer.
15. The method of claim 12 , wherein an operating pressure of the first deposition method is less than an operating pressure of the second deposition method.
16. The method of claim 12 , wherein a power consumption for depositing the third dielectric layer is greater than a power consumption for depositing the first dielectric layer.
17. The method of claim 12 , wherein the round corners have a radius of curvature between 0.01 μm and 0.2 μm.
18. The method of claim 12 , further comprising covering a first protection layer on the second metal layer, and forming a second protection layer on the first protection layer.