Wafer bonding method

1. A method comprising:

obtaining a first wafer comprising a first semiconductor substrate, a first dielectric layer, and first die connectors;

removing a first portion of the first dielectric layer in an edge region of the first wafer with a first trim process, the first trim process removing the first dielectric layer at a faster rate than the first semiconductor substrate;

removing a second portion of the first semiconductor substrate in the edge region of the first wafer with a second trim process, the second trim process removing the first semiconductor substrate at a faster rate than the first dielectric layer; and

bonding a second wafer to the first wafer, the second wafer comprising a second semiconductor substrate, a second dielectric layer, and second die connectors, the second dielectric layer bonded to the first dielectric layer with dielectric-to-dielectric bonds, the second die connectors bonded to the first die connectors with metal-to-metal bonds.

2. The method of claim 1 , wherein the first trim process removes the first portion of the first dielectric layer along a first direction, and the second trim process removes the second portion of the first semiconductor substrate along a second direction, the first direction different from the second direction.

3. The method of claim 2 , wherein the first direction forms an obtuse angle with the second direction, the second direction being perpendicular to an active surface of the first semiconductor substrate.

4. The method of claim 1 , wherein the first trim process is a chemical etching process and the second trim process is a sawing process.

5. The method of claim 1 , wherein the first trim process is a chemical etching process and the second trim process is a chemical or ablative etching process.

6. The method of claim 1 , wherein the first trim process is an ablative etching process and the second trim process is a sawing process.

7. The method of claim 1 , wherein the first trim process is an ablative etching process and the second trim process is a chemical or ablative etching process.

8. The method of claim 1 further comprising:

thinning the first semiconductor substrate to expose conductive vias of the first wafer and to remove a third portion of the first semiconductor substrate in the edge region of the first wafer.

9. The method of claim 8 further comprising:

obtaining a third wafer comprising a third semiconductor substrate, a third dielectric layer, and third die connectors; and

bonding the third wafer to the first wafer, the third dielectric layer bonded to the first semiconductor substrate with dielectric-to-dielectric bonds, the third die connectors bonded to the conductive vias with metal-to-metal bonds.

10. The method of claim 1 , wherein after the first trim process, the first dielectric layer has a reentrant profile shape.

11. A method comprising:

obtaining a first wafer comprising a semiconductor substrate and a dielectric layer;

removing edge regions of the dielectric layer with an etching process while a mask covers center regions of the dielectric layer, the etching process removing the edge regions of the dielectric layer along a first direction;

removing edge regions of the semiconductor substrate with a sawing process, the sawing process removing the edge regions of the semiconductor substrate along a second direction, second direction different from the first direction; and

bonding a second wafer to the first wafer.

12. The method of claim 11 , wherein the first direction forms an obtuse angle with the second direction, the second direction being perpendicular to an active surface of the semiconductor substrate.

13. The method of claim 11 , wherein after removing the edge regions of the dielectric layer, a width of the dielectric layer decreases continually in a direction extending away from an active surface of the semiconductor substrate.

14. A structure comprising:

a first wafer comprising a first semiconductor substrate, a first dielectric layer, and first die connectors, a sidewall of the first dielectric layer forming an obtuse angle with a sidewall of the first semiconductor substrate; and

a second wafer comprising a second semiconductor substrate, a second dielectric layer, and second die connectors, the second dielectric layer bonded to the first dielectric layer with dielectric-to-dielectric bonds, the second die connectors bonded to the first die connectors with metal-to-metal bonds, a sidewall of the second dielectric layer being laterally offset from the sidewall of the first dielectric layer.

15. The structure of claim 14 , wherein a sidewall of the second semiconductor substrate is laterally offset from the sidewall of the first semiconductor substrate.

16. The structure of claim 14 , wherein the sidewall of the first semiconductor substrate has a first portion and a second portion, the first portion connecting the second portion to an active surface of the first semiconductor substrate, the first portion forming the obtuse angle with the second portion.

17. The structure of claim 14 , wherein the sidewall of the first semiconductor substrate forms a right angle with an active surface of the first semiconductor substrate.

18. The structure of claim 14 , wherein the sidewall of the first semiconductor substrate forms an acute angle with an active surface of the first semiconductor substrate.

19. The structure of claim 14 , wherein the first wafer further comprises conductive vias extending through the first semiconductor substrate.

20. The structure of claim 14 , wherein a width of the first dielectric layer decreases continually in a direction extending away from an active surface of the first semiconductor substrate.