Integrated circuit product and chip floorplan arrangement thereof

1. An integrated circuit (IC) product ( 100 ; 200 ; 300 ), comprising:

a first chip ( 112 ; 212 ; 312 );

a second chip ( 114 ; 214 ; 314 );

a third chip ( 116 ; 216 ; 316 );

a fourth chip ( 118 ; 218 ; 318 );

a fifth chip ( 122 ; 222 ; 322 );

a sixth chip ( 124 ; 224 ; 324 );

a seventh chip ( 126 ; 226 ; 326 ); and

an eighth chip ( 128 ; 228 ; 328 );

wherein the first chip ( 112 ; 212 ; 312 ), the second chip ( 114 ; 214 ; 314 ), the third chip ( 116 ; 216 ; 316 ), and the fourth chip ( 118 ; 218 ; 318 ) have substantially identical area and constituent components;

the fifth chip ( 122 ; 222 ; 322 ), the sixth chip ( 124 ; 224 ; 324 ), the seventh chip ( 126 ; 226 ; 326 ), and the eighth chip ( 128 ; 228 ; 328 ) have substantially identical area and constituent components;

the first chip ( 112 ; 212 ; 312 ), the second chip ( 114 ; 214 ; 314 ), the third chip ( 116 ; 216 ; 316 ), and the fourth chip ( 118 ; 218 ; 318 ) are arranged on four sides of the IC product ( 100 ; 200 ; 300 ), respectively; and

the fifth chip ( 122 ; 222 ; 322 ), the sixth chip ( 124 ; 224 ; 324 ), the seventh chip ( 126 ; 226 ; 326 ), and the eighth chip ( 128 ; 228 ; 328 ) are arranged in a central area ( 160 ; 260 ; 360 ) of the IC product ( 100 ; 200 ; 300 );

wherein any chip of the first chip ( 112 ; 212 ; 312 ), the second chip ( 114 ; 214 ; 314 ), the third chip ( 116 ; 216 ; 316 ), and the fourth chip ( 118 ; 218 ; 318 ) is coupled to one of the fifth chip ( 122 ; 222 ; 322 ), the sixth chip ( 124 ; 224 ; 324 ), the seventh chip ( 126 ; 226 ; 326 ), and the eighth chip ( 128 ; 228 ; 328 ).

2. The IC product ( 100 ; 200 ; 300 ) of claim 1 , wherein a floorplan arrangement of the first chip ( 112 ; 212 ; 312 ), the second chip ( 114 ; 214 ; 314 ), the third chip ( 116 ; 216 ; 316 ), and the fourth chip ( 118 ; 218 ; 318 ) possesses point symmetry with respect to a center ( 101 ; 201 ; 301 ) of the IC product ( 100 ; 200 ; 300 ), and a floorplan arrangement of the fifth chip ( 122 ; 222 ; 322 ), the sixth chip ( 124 ; 224 ; 324 ), the seventh chip ( 126 ; 226 ; 326 ), and the eighth chip ( 128 ; 228 ; 328 ) possesses point symmetry with respect to the center ( 101 ; 201 ; 301 ).

3. The IC product ( 100 ; 200 ; 300 ) of claim 1 , wherein the first chip ( 112 ; 212 ; 312 ), the second chip ( 114 ; 214 ; 314 ), the third chip ( 116 ; 216 ; 316 ), and the fourth chip ( 118 ; 218 ; 318 ) are arranged in a circle.

4. The IC product ( 100 ) of claim 1 , wherein the first chip ( 112 ) is adjacent to the fourth chip ( 118 ) and the second chip ( 114 ), the second chip ( 114 ) is adjacent to the first chip ( 112 ) and the third chip ( 116 ), the third chip ( 116 ) is adjacent to the second chip ( 114 ) and the fourth chip ( 118 ), and the fourth chip ( 118 ) is adjacent to the third chip ( 116 ) and the first chip ( 112 ).

5. The IC product ( 100 ; 200 ; 300 ) of claim 1 , wherein the first chip ( 112 ; 212 ; 312 ), the second chip ( 114 ; 214 ; 314 ), the third chip ( 116 ; 216 ; 316 ), and the fourth chip ( 118 ; 218 ; 318 ) are logic chips, and the fifth chip ( 122 ; 222 ; 322 ), the sixth chip ( 124 ; 224 ; 324 ), the seventh chip ( 126 ; 226 ; 326 ), and the eighth chip ( 128 ; 228 ; 328 ) are memory chips.

6. The IC product ( 100 ) of claim 1 , wherein the first chip ( 112 ) and the fifth chip ( 122 ) form a first polygon ( 132 ), and the second chip ( 114 ) and the sixth chip ( 124 ) form a second polygon ( 134 ), and if the first polygon ( 132 ) is rotated ninety degrees with respect to a center ( 101 ) of the IC product ( 100 ), the first polygon ( 132 ) will completely overlap with the second polygon ( 134 ).

7. The IC product ( 100 ) of claim 1 , wherein the fourth chip ( 118 ) and the fifth chip ( 122 ) form a third polygon ( 136 ), and the first chip ( 112 ) and the sixth chip ( 124 ) form a fourth polygon ( 138 ), and if the third polygon ( 136 ) is rotated ninety degrees with respect to a center ( 101 ) of the IC product ( 100 ), the third polygon ( 136 ) will completely overlap with the fourth polygon ( 138 ).

8. The IC product ( 100 ; 200 ; 300 ) of claim 1 , wherein the first chip ( 112 ; 212 ; 312 ), the second chip ( 114 ; 214 ; 314 ), the third chip ( 116 ; 216 ; 316 ), and the fourth chip ( 118 ; 218 ; 318 ) collectively surround the central area ( 160 ; 260 ; 360 ).

9. The IC product ( 100 ; 200 ) of claim 8 , wherein the first chip ( 112 ; 212 ), the second chip ( 114 ; 214 ), the third chip ( 116 ; 216 ), and the fourth chip ( 118 ; 218 ) completely enclose the central area ( 160 ; 260 ).

10. The IC product ( 200 ; 300 ) of claim 1 further comprising:

a ninth chip ( 232 ; 332 );

a tenth chip ( 234 ; 334 );

an eleventh chip ( 236 ; 336 ); and

a twelfth chip ( 238 ; 338 );

wherein the ninth chip ( 232 ; 332 ), the tenth chip ( 234 ; 334 ), the eleventh chip ( 236 ; 336 ), and the twelfth chip ( 238 ; 338 ) are arranged outside the central area ( 260 ; 360 ).

11. The IC product ( 200 ) of claim 10 , wherein the ninth chip ( 232 ), the tenth chip ( 234 ), the eleventh chip ( 236 ), and the twelfth chip ( 238 ) are arranged at four corners of the IC product ( 200 ).

12. The IC product ( 300 ) of claim 10 , wherein the first chip ( 312 ), the second chip ( 314 ), the third chip ( 316 ), and the fourth chip ( 318 ) are arranged at four corners of the IC product ( 300 ).

13. The IC product ( 200 ; 300 ) of claim 10 , wherein the first chip ( 212 ; 312 ), the fifth chip ( 222 ; 322 ), and the ninth chip ( 232 ; 332 ) form a first polygon ( 132 ), the second chip ( 214 ; 314 ), the sixth chip ( 224 ; 324 ), and the tenth chip ( 234 ; 334 ) form a second polygon ( 134 ), and if the first polygon ( 132 ) is rotated ninety degrees with respect to a center ( 201 ; 301 ) of the IC product ( 200 ; 300 ), the first polygon ( 132 ) will completely overlap with the second polygon ( 134 ).

14. The IC product ( 200 ; 300 ) of claim 10 , wherein the fourth chip ( 218 ; 318 ), the fifth chip ( 222 ; 322 ), and the twelfth chip ( 238 ; 338 ) form a third polygon ( 136 ), the first chip ( 212 ; 312 ), the sixth chip ( 224 ; 324 ), and the ninth chip ( 232 ; 332 ) form a fourth polygon ( 138 ), and if the third polygon ( 136 ) is rotated ninety degrees with respect to a center ( 201 ; 301 ) of the IC product ( 200 ; 300 ), the third polygon ( 136 ) will completely overlap with the fourth polygon ( 138 ).

15. An integrated circuit (IC) product ( 100 ; 200 ; 300 ) having a first side ( 102 ; 202 ; 302 ), a second side ( 104 ; 204 ; 304 ), a third side ( 106 ; 206 ; 306 ), and a fourth side ( 108 ; 208 ; 308 ), comprising:

a first logic chip ( 112 ; 212 ; 312 ), arranged on the first side ( 102 ; 202 ; 302 );

a second logic chip ( 114 ; 214 ; 314 ), arranged on the second side ( 104 ; 204 ; 304 );

a third logic chip ( 116 ; 216 ; 316 ), arranged on the third side ( 106 ; 206 ; 306 );

a fourth logic chip ( 118 ; 218 ; 318 ), arranged on the fourth side ( 108 ; 208 ; 308 );

a first memory chip ( 122 ; 222 ; 322 );

a second memory chip ( 124 ; 224 ; 324 );

a third memory chip ( 126 ; 226 ; 326 ); and

a fourth memory chip ( 128 ; 228 ; 328 );

wherein a floorplan arrangement of the first logic chip ( 112 ; 212 ; 312 ), the second logic chip ( 114 ; 214 ; 314 ), the third logic chip ( 116 ; 216 ; 316 ), and the fourth logic chip ( 118 ; 218 ; 318 ) possesses point symmetry with respect to a center ( 101 ; 201 ; 301 ) of the IC product ( 100 ; 200 ; 300 ), and a floorplan arrangement of the first memory chip ( 122 ; 222 ; 322 ), the second memory chip ( 124 ; 224 ; 324 ), the third memory chip ( 126 ; 226 ; 326 ), and the fourth memory chip ( 128 ; 228 ; 328 ) possesses point symmetry with respect to the center ( 101 ; 201 ; 301 );

wherein any chip of the first logic chip ( 112 ; 212 ; 312 ), the second logic chip ( 114 ; 214 ; 314 ), the third logic chip ( 116 ; 216 ; 316 ), and the fourth logic chip ( 118 ; 218 ; 318 ) is coupled to one of the first memory chip ( 122 ; 222 ; 322 ), the second memory chip ( 124 ; 224 ; 324 ), the third memory chip ( 126 , 226 , 326 ), and the fourth memory chip ( 128 , 228 , 328 ).

16. The IC product ( 100 ; 200 ; 300 ) of claim 15 , wherein the first logic chip ( 112 ; 212 ; 312 ), the second logic chip ( 114 ; 214 ; 314 ), the third logic chip ( 116 ; 216 ; 316 ), and the fourth logic chip ( 118 ; 218 ; 318 ) are substantially identical in area.

17. The IC product ( 100 ; 200 ; 300 ) of claim 15 , wherein the first memory chip ( 122 ; 222 ; 322 ), the second memory chip ( 124 ; 224 ; 324 ), the third memory chip ( 126 ; 226 ; 326 ), and the fourth memory chip ( 128 ; 228 ; 328 ) are substantially identical in area.

18. The IC product ( 100 ; 200 ; 300 ) of claim 15 , wherein the first logic chip ( 112 ; 212 ; 312 ), the second logic chip ( 114 ; 214 ; 314 ), the third logic chip ( 116 ; 216 ; 316 ), and the fourth logic chip ( 118 ; 218 ; 318 ) are arranged in a circle.

19. The IC product ( 100 ; 200 ; 300 ) of claim 15 , wherein the first logic chip ( 112 ; 212 ; 312 ), the second logic chip ( 114 ; 214 ; 314 ), the third logic chip ( 116 ; 216 ; 316 ), and the fourth logic chip ( 118 ; 218 ; 318 ) collectively surround a central area ( 160 ; 260 ; 360 ) of the IC product ( 100 ; 200 ; 300 ).

20. The IC product ( 100 ; 200 ) of claim 19 , wherein the first logic chip ( 112 ; 212 ), the second logic chip ( 114 ; 214 ), the third logic chip ( 116 ; 216 ), and the fourth logic chip ( 118 ; 218 ) completely enclose the central area ( 160 ; 260 ).