IP Library Granted Patent US 11,973,106
Granted Patent B2
US 11,973,106 · App. 17/857,472 · Granted Apr 30, 2024

Semiconductor device and method for manufacturing the same

Inventors: Jae Hee Song (Gyeonggi-do, KR); Dong Hyun Lee (Gyeonggi-do, KR); Kyung Woong Park (Gyeonggi-do, KR); Cheol Hwan Park (Gyeonggi-do, KR); Ki Vin Im (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H01L28/91H01L28/75H01L28/90H10B12/033
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Quick Facts
Patent No.
US 11,973,106
App. No.
17/857,472
Granted
Apr 30, 2024
Kind
B2
Abstract

A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

Claims (36)

1. A semiconductor device comprising:

a lower electrode;

a supporter supporting an outer wall of the lower electrode;

a dielectric layer formed on the lower electrode and the supporter;

an upper electrode on the dielectric layer;

a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and

a second interfacial layer disposed between the dielectric layer and the upper electrode,

wherein the first interfacial layer is a stack of niobium oxide contacting the lower electrode and niobium nitride contacting the dielectric layer.

2. The semiconductor device of claim 1 ,

wherein the dielectric layer and the supporter are in direct contact with each other, and

wherein the first interfacial layer is not disposed in an interfacial layer-free part of the semiconductor device.

3. The semiconductor device of claim 1 ,

wherein the niobium nitride includes a material obtained by selectively nitriding a portion of the niobium oxide.

4. The semiconductor device of claim 1 ,

wherein the dielectric layer includes hafnium oxide having a tetragonal structure.

5. The semiconductor device of claim 1 ,

wherein the dielectric layer includes zirconium oxide, hafnium oxide, ferroelectric material, antiferroelectric material, HfZrO, a ZAZ (ZrO2/Al2O3/ZrO2) stack, a ZAZA (ZrO2/Al2O3/ZrO2/Al2O3) stack, a ZAZAT (ZrO2/Al2O3/ZrO2/Al2O3/TiO2) stack, a HAH (HfO2/Al2O3/HfO2) stack, a TiO2/ZrO2/Al2O3/ZrO2 stack, a TiO2/HfO2/Al2O3/HfO2 stack, a Ta2O5/ZrO2/Al2O3/ZrO2 stack, a Ta2O5/HfO2/Al2O3/HfO2 stack, a HZAZH (HfO2/ZrO2/Al2O3/ZrO2/HfO2) stack, a HZAZHA (HfO2/ZrO2/Al2O3/ZrO2/HfO2/Al2O3) stack, a ZAH (ZrO2/Al2O3/HfO2) stack, a HAZ (HfO2/Al2O3/ZrO2) stack, a ZHAZHAT (ZrO2/HfO2/Al2O3/ZrO2/HfO2/Al2O3/TiO2) stack or a combination thereof.

6. The semiconductor device of claim 1 ,

wherein the lower electrode has a cylindrical shape, a pillar shape, or a combination thereof.

7. The semiconductor device of claim 1 ,

wherein the first interfacial layer and the second interfacial layer include the same material.

8. The semiconductor device of claim 1 ,

wherein the second interfacial layer includes a stack of niobium oxide and niobium nitride,

wherein the niobium oxide contacts the dielectric layer, and

wherein the niobium nitride contacts the upper electrode.

9. The semiconductor device of claim 1 ,

the second interfacial layer includes a stack of niobium oxide and niobium oxynitride,

wherein the niobium oxide contacts the dielectric layer, and

wherein the niobium oxynitride contacts the upper electrode.

10. The semiconductor device of claim 1 ,

wherein the second interfacial layer includes one metal selected from a group consisting of tantalum, titanium, yttrium and molybdenum, and

wherein the second interfacial layer includes an oxide of the metal, a nitride of the metal, an oxynitride of the metal, or a combination thereof.

11. The semiconductor device of claim 1 ,

wherein the supporter includes a multi-layered level supporter,

wherein the dielectric layer and the multi-layered level supporter are in direct contact with each other, and

wherein the first interfacial layer is not disposed in an interfacial layer-free part of the semiconductor device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2022
From: SONG, JAE HEE; LEE, DONG HYUN; PARK, KYUNG WOONG; PARK, CHEOL HWAN; IM, KI VIN
To: SK HYNIX INC.
Reel/Frame 060398/0609 →
Priority Claims (1)
KR 10-2021-0193331 · Dec 30, 2021 · national
Continuity (1)
Related Publication 20230215910A1 · Jul 6, 2023
Cited By (1)
US 12,701,689