Array substrate and display apparatus

1. An array substrate, comprising:

a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit; and

a first voltage supply line, a second voltage supply line, and a third voltage supply line configured to provide a constant voltage signal respectively to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit;

wherein the first voltage signal line crosses over a second capacitor electrode in the first pixel driving circuit by a first overlapping area;

the second voltage supply line crosses over a second capacitor electrode in the second pixel driving circuit by a second overlapping area;

the third voltage supply line crosses over a second capacitor electrode in the third pixel driving circuit by a third overlapping area; and

the third overlapping area is greater than the first overlapping area, and is greater than the second overlapping area.

2. The array substrate of claim 1 , further comprising a semiconductor material layer comprising active layers of one or more transistors in the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit;

wherein the first voltage signal line crosses over the semiconductor material layer in the first pixel driving circuit by a fourth overlapping area;

the second voltage supply line crosses over the semiconductor material layer in the second pixel driving circuit by a fifth overlapping area;

the third voltage supply line crosses over the semiconductor material layer in the third pixel driving circuit by a sixth overlapping area; and

the sixth overlapping area is greater than the fourth overlapping area, and is greater than the fifth overlapping area.

3. The array substrate of claim 1 , further comprising:

a first data line, a second data line, and a third data line configured to provide data signals respectively to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit;

a first light emitting element, a second light emitting element, and a third light emitting element respectively connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit;

wherein a first virtual line and a second virtual line respectively cross over the first voltage supply line, the second voltage supply line, and the third voltage supply line;

the first voltage supply line, the second voltage supply line, and the third voltage supply line respectively comprise a first voltage supply line portion, a second voltage supply line portion, and a third voltage supply line portion, respectively between the first virtual line and the second virtual line;

an orthographic projection of a third anode of the third light emitting element on a base substrate completely covers an orthographic projection of the third voltage supply line portion on the base substrate; and

the third voltage supply line portion has a third line width greater than a first line width of the first voltage supply line portion, and greater than a second line width of the second voltage supply line portion.

4. The array substrate of claim 3 , wherein the first virtual line and the second virtual line further respectively cross over the first data line, the second data line, the third data line;

the first data line, the second data line, the third data line respectively comprise a first data line portion, a second data line portion, a third data line portion, respectively between the first virtual line and the second virtual line; and

the first data line portion, the second data line portion, and the third data line portion have a substantially same line width.

5. The array substrate of claim 4 , wherein the orthographic projection of the third anode on the base substrate is at least partially overlapping with an orthographic projection of the third data line portion on the base substrate.

6. The array substrate of claim 3 , wherein the first data line, the second data line, the third data line, the first voltage supply line, the second voltage supply line, and the third voltage supply line are substantially parallel to each other; and

data lines and voltage supply lines are alternatively arranged.

7. The array substrate of claim 3 , wherein the third voltage supply line portion comprises a main sub-portion and a widening sub-portion;

the main sub-portion is between the widening sub-portion and the third data line; and

the main sub-portion, the first voltage supply line portion, and the second voltage supply line portion have a same shape.

8. The array substrate of claim 7 , wherein the main sub-portion, the first voltage supply line portion, and the second voltage supply line portion have a same shape and a same width.

9. The array substrate of claim 3 , wherein a first anode of the first light emitting element is between the first voltage supply line and the second data line; and

a second anode of the second light emitting element is between the first voltage supply line and the second data line.

10. The array substrate of claim 9 , wherein an orthographic projection of the first anode on the base substrate at least partially overlaps with an orthographic projection of the first data line on the base substrate and at least partially overlaps with an orthographic projection of the second voltage supply line on the base substrate; and

an orthographic projection of the second anode on the base substrate at least partially overlaps with an orthographic projection of the first data line on the base substrate and at least partially overlaps with an orthographic projection of the second voltage supply line on the base substrate.

11. The array substrate of claim 10 , wherein the orthographic projection of the first anode on the base substrate further at least partially overlaps with an orthographic projection of the first voltage supply line on the base substrate; and

the orthographic projection of the second anode on the base substrate at least partially overlaps with an orthographic projection of the first voltage supply line on the base substrate.

12. The array substrate of claim 9 , further comprising:

a first anode contact pad, a second anode contact pad, and a third anode contact pad;

a planarization layer on a side of the first anode contact pad, the second anode contact pad, and the third anode contact pad away from the base substrate;

a first anode contact hole, a second anode contact hole, a third anode contact hole respectively extending through the planarization layer;

a pixel definition layer on a side of the first anode, the second anode, and the third anode away from the planarization layer;

a first subpixel aperture, a second subpixel aperture, and a third subpixel aperture respectively extending through the pixel definition layer; and

a first light emitting layer, a second light emitting layer, and a third light emitting layer on a side of the pixel definition layer away from the base substrate;

wherein the first anode, the second anode, and the third anode are respectively connected to the first anode contact pad, the second anode contact pad, and the third anode contact pad, respectively through the first anode contact hole, the second anode contact hole, and the third anode contact hole; and

the first light emitting layer, the second light emitting layer, and the third light emitting layer are respectively connected to the first anode, the second anode, and the third anode, respectively through the first subpixel aperture, the second subpixel aperture, and the third subpixel aperture.

13. The array substrate of claim 12 , wherein the first anode contact hole is outside a region having the first subpixel aperture;

the second anode contact hole is outside a region having the second subpixel aperture; and

the third anode contact hole is outside a region having the third subpixel aperture.

14. The array substrate of claim 12 , further comprising at least one insulating layer between the base substrate and the first anode contact pad, the second anode contact pad, and the third anode contact pad;

a first pad contact via, a second pad contact via, and a third pad contact via respectively extending through the at least one insulating layer; and

the first anode contact pad, the second anode contact pad, and the third anode contact pad are respectively connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively through the first pad contact via, the second pad contact via, and the third pad contact via.

15. The array substrate of claim 14 , wherein, along a direction of the first virtual line or the second virtual line, the first anode contact hole is between the first pad contact via and the first voltage supply line;

along the direction of the first virtual line or the second virtual line, the second anode contact hole is between the second pad contact via and the second voltage supply line; and

the third pad contact via and the third anode contact hole are arranged along a direction substantially parallel to the third data line and the third voltage supply line.

16. The array substrate of claim 9 , wherein the first anode comprises a first main portion and a first bridge portion;

the second anode comprises a second main portion and a second bridge portion;

the third anode comprises a third main portion and a third bridge portion;

the first main portion, the second main portion, and the third main portion have a substantially rectangular shape; and

the first bridge portion, the second bridge portion, and the third bridge portion respectively protruding outward from the first main portion, the second main portion, and the third main portion.

17. The array substrate of claim 16 , further comprising:

a first anode contact pad, a second anode contact pad, and a third anode contact pad;

a planarization layer on a side of the first anode contact pad, the second anode contact pad, and the third anode contact pad away from the base substrate;

a first anode contact hole, a second anode contact hole, a third anode contact hole respectively extending through the planarization layer;

wherein the first bridge portion, the second bridge portion, and the third bridge portion are respectively connected to the first anode contact pad, the second anode contact pad, and the third anode contact pad, respectively through the first anode contact hole, the second anode contact hole, and the third anode contact hole.

18. The array substrate of claim 16 , wherein the third bridge portion protrudes outward from the third main portion along a direction substantially parallel to the first virtual line or the second virtual line;

the second bridge portion protrudes outward from the second main portion along a direction substantially parallel to the second data line or the second voltage supply line; and

the first bridge portion protrudes outward from the first main portion along a direction at an angle oblique to the first virtual line and to the first data line.

19. The array substrate of claim 3 , wherein the first data line, the second data line, and the third data line further configured to provide the data signals respectively to a fourth pixel driving circuit, a fifth pixel driving circuit, and a sixth pixel driving circuit;

the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit are sequentially arranged along a direction substantially parallel to the first virtual line or the second virtual line;

the fourth pixel driving circuit, the fifth pixel driving circuit, and the sixth pixel driving circuit are sequentially arranged along the direction substantially parallel to the first virtual line or the second virtual line;

the first pixel driving circuit and the fourth pixel driving circuit are arranged along a direction substantially parallel to the first data line or the first voltage supply line;

the second pixel driving circuit and the fifth pixel driving circuit are arranged along a direction substantially parallel to the second data line or the second voltage supply line; and

the third pixel driving circuit and the sixth pixel driving circuit are arranged along a direction substantially parallel to the third data line or the third voltage supply line.

20. A display apparatus, comprising the array substrate of claim 1 , and an integrated circuit connected to the array substrate.