IP Library › Granted Patent US 11,978,496
Granted Patent B2
US 11,978,496 · App. 17/730,333 · Granted May 7, 2024

Distributed global and local reference voltage generation

Inventors: Jiwang Lee (San Jose, CA); Jaewon Lee (Santa Clara, CA); Po-Chien Chiang (Hsinchu, TW); Hsuche Nee (Zhubei, TW); Wen-Hung Lo (Saratoga, CA); Michael Ivan Halfen (San Francisco, CA); Abhishek Dhir (Mississauga, CA)
Assignee: NVIDIA CORP.
G11C11/4074
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Quick Facts
Patent No.
US 11,978,496
App. No.
17/730,333
Granted
May 7, 2024
Kind
B2
Abstract

A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.

Claims (20)

1. A circuit comprising:

a global reference voltage generator comprising a differential voltage output and a first N-bit control input;

a local reference voltage generator coupled to receive the differential output of the global reference voltage generator, the local reference voltage generator comprising an M-bit control input, where M, N>1; and

the local reference voltage generator comprising a voltage ladder coupled between an upper reference voltage line of the differential output and a lower reference voltage line of the differential output.

2. The circuit of claim 1 , wherein M<N.

3. The circuit of claim 1 , the global reference voltage generator further comprising a second N-bit control input.

4. The circuit of claim 3 , wherein the first N-bit control input sets an upper reference voltage on the differential output.

5. The circuit of claim 3 , wherein the second N-bit control input sets a lower reference voltage on the differential output.

6. The circuit of claim 1 , the local reference voltage generator further comprising a plurality of multiplexers, each multiplexer coupled to the voltage ladder and comprising a control input to select one of a plurality of voltage outputs from the voltage ladder.

7. The circuit of claim 6 , each of the multiplexers coupled to provide a selected reference voltage to an input/output (TO) circuit of a different rank of a memory circuit.

8. A circuit comprising:

a number of ranks Y, each rank being X bits wide;

a global reference voltage generator comprising a differential voltage output;

a number X of local reference voltage generators coupled to receive the differential output of the global reference voltage generator, each local reference voltage generator configured to generate Y independently configurable reference voltages; and

wherein the Y reference voltages of each local reference voltage generator are each provided to a different rank of the circuit.

9. The circuit of claim 8 , wherein an upper voltage of the differential voltage output of the global reference voltage generator is configurable with a first N-bit control signal, and a lower voltage of the differential voltage output of the global reference voltage generator is configurable with a second N-bit control signal.

10. The circuit of claim 9 , wherein the local reference voltage generator outputs are each configurable with a control signal comprising M-bits, where M N.

11. The circuit of claim 8 , wherein one or more of the local reference voltage generators comprises a plurality of multiplexers each coupled to receive a plurality of inputs from a shared voltage ladder.

12. The circuit of claim 11 , the voltage ladder coupled across the differential output of the global reference voltage generator.

13. The circuit of claim 11 , each of the local reference voltage generators co-located, on a die for the circuit, with an IO circuit to which they provide a reference voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2022
From: LEE, JIWANG; LEE, JAEWON; CHIANG, PO-CHIEN; NEE, HSUCHE; LO, WEN-HUNG; HALFEN, MICHAEL IVAN; DHIR, ABHISHEK
To: NVIDIA CORP.
Reel/Frame 059888/0608 →
Continuity (1)
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