Semiconductor memory devices with differential threshold voltages

1. A memory device, comprising:

a non-volatile memory cell;

wherein the non-volatile memory cell includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled in series;

wherein the first transistor has a first threshold voltage and the second transistor has a second threshold voltage, the first threshold voltage being different from the second threshold voltage; and

wherein the first transistor and the second transistor have different high-k gate dielectric layers.

2. The memory device of claim 1 , wherein the resistor has a first terminal connected to a bit line (BL) and a second terminal connected to a first source/drain terminal of the first transistor, the first transistor has a second source/drain terminal connected to a first source/drain terminal of the second transistor, and the second transistor has a second source/drain terminal connected to a source line (SL).

3. The memory device of claim 2 , wherein a gate terminal of the first transistor is connected to a word line (WL) and a gate terminal of the second transistor is connected to the WL.

4. The memory device of claim 3 , wherein the second transistor is configured to provide a negative Vgs for the first transistor, in response to the WL being not asserted.

5. The memory device of claim 2 , wherein the second threshold voltage is greater than the first threshold voltage.

6. The memory device of claim 1 , wherein the first and second transistors have respective different work function layers.

7. The memory device of claim 1 , wherein the first and second transistors have their channels doped in respective different concentrations.

8. The memory device of claim 1 , wherein the first and second transistors are both n-type transistors.

9. The memory device of claim 1 , wherein the first and second transistors are both p-type transistors.

10. A memory device, comprising:

a plurality of resistive random access memory (RRAM) cells commonly connected between a bit line (BL) and a source line (SL);

wherein each of the RRAM cells includes a resistor, a first transistor, and a second transistor coupled to each other in series, with the resistor connected to the BL and the second transistor connected to the SL;

wherein the first transistor has a first threshold voltage and the second transistor has a second threshold voltage, the first threshold voltage being less than the second threshold voltage; and

wherein the first transistor and the second transistor have different work function layers.

11. The memory device of claim 10 , wherein a gate terminal of the first transistor is connected to a word line (WL) and a gate terminal of the second transistor is connected to the WL.

12. The memory device of claim 10 , wherein the second transistor of each unselected one of the plurality of RRAM cells is configured to increase a voltage level at a node connected between the first and second transistors of the unselected RRAM cell.

13. The memory device of claim 12 , wherein the voltage level is greater than zero.

14. The memory device of claim 10 , wherein the first and second transistors have respective different high-k gate dielectric layers.

15. The memory device of claim 10 , wherein the first and second transistors have their channels doped in respective different concentrations.

16. A method for accessing a memory device, comprising:

providing a plurality of memory cells coupled between a bit line (BL) and a source line (SL), wherein each of the plurality of memory cells comprises a resistor operatively coupled to the BL, a first transistor connected to the resistor in series, and a second transistor connected to the first transistor in series and operatively coupled to the SL; and

reading one of the plurality of memory cells by at least performing: (i) asserting one of a plurality of word lines (WLs) that gates the first and second transistors of the memory cell; and (ii) deasserting remaining ones of the plurality of WLs that gate the respective first and second transistors of remaining ones of the plurality of memory cells;

wherein respective nodes connected between the first and second transistor of each of the remaining memory cells have a voltage level greater than zero.

17. The method of claim 16 , wherein the resistor of each of the memory cells has a variable resistance.

18. The method of claim 16 , wherein the first transistor has a first threshold voltage and the second transistor has a second threshold voltage, and wherein the second threshold voltage is greater than the first threshold voltage.

19. The method of claim 16 , wherein the first and second transistors have different high-k gate dielectric layers.

20. The method of claim 16 , wherein the first and second transistors have different work function layers.