Semiconductor device

1. A semiconductor device, comprising:

a substrate;

an active pattern extending in a first direction on the substrate;

first and second nanosheets stacked on the active pattern to be spaced apart from each other in a vertical direction;

a gate electrode that extends in a second direction different from the first direction on the active pattern, the gate electrode surrounding each of the first and second nanosheets;

a source/drain region on at least one side of the gate electrode; and

inner spacers between the gate electrode and the source/drain region, the inner spacers including:

a first inner spacer between the active pattern and the first nanosheet, and

a second inner spacer between the first nanosheet and the second nanosheet, the second inner spacer having:

a first portion adjacent to the first nanosheet, and

a second portion adjacent to the second nanosheet, a width of the first portion of the second inner spacer in the first direction being greater than a width of the second portion of the second inner spacer in the first direction,

wherein at least a part of the first portion of the second inner spacer extends farther into the source/drain region than the second portion of the second inner spacer.

2. The semiconductor device as claimed in claim 1 , further comprising a source/drain contact on the source/drain region and extending into the source/drain region, a first pitch in the first direction between the first portion of the second inner spacer and the source/drain contact being smaller than a second pitch in the first direction between the second portion of the second inner spacer and the source/drain contact.

3. The semiconductor device as claimed in claim 2 , wherein a lower surface of the source/drain contact is on a same plane as a lower surface of the second inner spacer.

4. The semiconductor device as claimed in claim 2 , wherein a lower surface of the source/drain contact is on a same plane as a lower surface of the first inner spacer.

5. The semiconductor device as claimed in claim 1 , wherein the second portion of the second inner spacer is between the first nanosheet and the second nanosheet.

6. The semiconductor device as claimed in claim 1 , wherein the at least part of the first portion of the second inner spacer that extends into the source/drain region does not overlap the second portion of the second inner spacer in the vertical direction.

7. The semiconductor device as claimed in claim 1 , wherein at least a part of the first inner spacer extends into the source/drain region.

8. The semiconductor device as claimed in claim 1 , wherein a side wall of the second portion of the second inner spacer has a continuous slope profile with a side wall of the second nanosheet.

9. The semiconductor device as claimed in claim 1 , wherein:

the first inner spacer includes a first portion adjacent to the active pattern, and a second portion adjacent to the first nanosheet, and

a width of the first portion of the first inner spacer in the first direction is greater than a width of the second portion of the first inner spacer in the first direction.

10. The semiconductor device as claimed in claim 1 , wherein:

each of the at least a part of the first portion of the second inner spacer and at least a part of the second portion of the second inner spacer extends into the source/drain region, and

a side wall of the second portion of the second inner spacer has a continuous slope profile with a side wall of the first portion of the second inner spacer.

11. The semiconductor device as claimed in claim 1 , wherein a side wall of the second nanosheet is recessed toward the gate electrode further than a side wall of the second portion of the second inner spacer.

12. A semiconductor device, comprising:

a substrate;

an active pattern extending in a first direction on the substrate;

nanosheets stacked on the active pattern to be spaced apart from each other in a vertical direction;

a gate electrode in a second direction different from the first direction on the active pattern, the gate electrode surrounding each of the nanosheets;

a source/drain region on at least one side of the gate electrode;

inner spacers between the gate electrode and the source/drain region, the inner spacers extending into the source/drain region; and

a source/drain contact on the source/drain region, the source/drain contact extending into the source/drain region and overlapping an uppermost one of the inner spacers in the first direction, the uppermost one of the inner spacers including:

a first portion, and

a second portion on an upper surface of the first portion, a first pitch in the first direction between the first portion and the source/drain contact being smaller than a second pitch in the first direction between the second portion and the source/drain contact.

13. The semiconductor device as claimed in claim 12 , wherein a width of the first portion of the uppermost one of the inner spacers in the first direction is greater than a width of the second portion of the uppermost one of the inner spacers in the first direction.

14. The semiconductor device as claimed in claim 12 , wherein at least a part of the first portion of the uppermost one of the inner spacers extending into the source/drain region does not overlap the second portion of the uppermost one of the inner spacers in the vertical direction.

15. The semiconductor device as claimed in claim 12 , wherein a side wall of the second portion of the uppermost one of the inner spacers has a continuous slope profile with a side wall of an uppermost one of the nanosheets.

16. The semiconductor device as claimed in claim 12 , wherein a lower surface of the source/drain contact is on a same plane as a lower surface of the uppermost one of the inner spacers.

17. A semiconductor device, comprising:

a substrate including a NMOS region and a PMOS region;

first nanosheets extending in a first direction on the NMOS region of the substrate, the first nanosheets being stacked to be spaced apart from each other in a vertical direction;

second nanosheets extending in the first direction on the PMOS region of the substrate, the second nanosheets being stacked to be spaced apart from each other in the vertical direction;

a first gate electrode extending on the NMOS region of the substrate in a second direction different from the first direction, the first gate electrode surrounding each of the first nanosheets;

a second gate electrode extends on the PMOS region of the substrate in the second direction, the second gate electrode surrounding each of the second nanosheets;

a first source/drain region on at least one side of the first gate electrode;

a second source/drain region on at least one side of the second gate electrode; and

first inner spacers between the first gate electrode and the first source/drain region, the first inner spacers extending into the first source/drain region, and an uppermost one of the first inner spacers having:

a first portion, and

a second portion on an upper surface of the first portion, a width of the first portion in the first direction being greater than a width of the second portion in the first direction,

wherein the first portion extends farther toward the first source/drain region than the second portion.

18. The semiconductor device as claimed in claim 17 , further comprising second inner spacers between the second gate electrode and the second source/drain region, the second inner spacers extending into the second source/drain region.

19. The semiconductor device as claimed in claim 18 , wherein an uppermost one of the second inner spacers includes:

a third portion; and

a fourth portion on an upper surface of the third portion, a width of the third portion in the first direction being greater than a width of the fourth portion in the first direction.

20. The semiconductor device as claimed in claim 17 , further comprising a gate insulating film between the second gate electrode and the second source/drain region, the gate insulating film being in contact with the second source/drain region.