Semiconductor device
Provided is a ferroelectric semiconductor device including a source and a drain having different polarities. The ferroelectric semiconductor may include a ferroelectric including zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), and/or hafnium-zirconium oxide (Hf x Zr 1-x O, 0<x<1). The semiconductor device may have memory-like characteristics.
1. A semiconductor device comprising:
a substrate including a source, a drain, and a channel between the source and the drain;
a gate electrode above the substrate; and
a ferroelectric between the substrate and the gate electrode,
wherein the source and the drain are doped to have different polarities from each other,
the ferroelectric comprises a base material and a dopant material,
the base material includes one or more selected from the group consisting of zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), and hafnium-zirconium oxide (Hf x Zr 1-x O, 0<x<1),
the dopant material comprises one or more materials selected from the group consisting of C, Si, Ge, Sn, Pb, Al, Y, La, Gd, Mg, Ca, Sr Ba, Ti, Zr, and Hf,
a content of the dopant material of the ferroelectric is greater than 0 at % and less than or equal to 6 at %, with respect to metal elements of the base material, and
a thickness of the ferroelectric is greater than 0 nm and less than or equal to about 20 nm.
2. The semiconductor device of claim 1 ,
wherein a ratio of an erase time to a programming time of the semiconductor device is about 0.8 to about 5.0.
3. The semiconductor device of claim 1 ,
wherein a programming time of the semiconductor device and an erase time of the semiconductor device are each 1,200 ns or less.
4. The semiconductor device of claim 1 ,
wherein the ferroelectric comprises an orthorhombic crystal phase.
5. The semiconductor device of claim 1 ,
wherein the substrate comprises one or more selected from the group consisting of Si, Ge, SiGe, and a group III-V semiconductor.
6. The semiconductor device of claim 1 ,
wherein the substrate is a silicon-on-insulator (SOI) substrate including a lower silicon layer, a silicon oxide layer, and an upper silicon layer, and
the source, the drain, and the channel are in the upper silicon layer.
7. The semiconductor device of claim 6 , further comprising:
a dielectric layer between the substrate and the ferroelectric.
8. The semiconductor device of claim 7 , further comprising:
a conductive layer between the dielectric layer and the ferroelectric, wherein
a cross-sectional area of the gate electrode is less than a cross-sectional area of the conductive layer.
9. The semiconductor device of claim 1 ,
wherein the channel comprises a semiconductor material different from a semiconductor material of the substrate.
10. The semiconductor device of claim 1 ,
wherein the channel comprises one or more selected from the group consisting of Si, Ge, SiGe, a group III-V material, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) material, a quantum dot, and an organic semiconductor.
11. The semiconductor device of claim 1 , further comprising:
a dielectric layer between the substrate and the ferroelectric.
12. The semiconductor device of claim 11 ,
wherein the dielectric layer comprises a paraelectric material or a high-k dielectric material.
13. The semiconductor device of claim 11 ,
wherein the dielectric layer comprises one or more selected from the group consisting of aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ), silicon oxide (SiO 2 ).
14. The semiconductor device of claim 11 , further comprising:
a conductive layer between the substrate and the ferroelectric.
15. The semiconductor device of claim 1 , wherein a region of the substrate between the source and the drain does not comprise a doping material.
16. The semiconductor device of claim 1 , wherein
a region of the substrate between the source and the drain is doped to have a same polarity as a polarity of the source or the drain, and
a concentration of a doping material in the region of the substrate between the source and the drain is less than a dopant concentration the source or a dopant concentration in the drain.
17. The semiconductor device of claim 16 ,
wherein the concentration of the doping material in the region between the source and the drain is 1×10 19 /cm 3 or less.
18. The semiconductor device of claim 1 ,
wherein the semiconductor device has memory-like characteristics.
19. An electronic device comprising:
the semiconductor device of claim 1 .
20. The semiconductor device of claim 1 , wherein a width of the ferroelectric is greater than a width of the channel.