Input signal shaping for a programmable logic array
A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.
1. An integrated circuit, comprising:
a programmable logic array having a data input; and
a signal conditioner including:
an input;
an edge detector;
a first multiplexer having a first input coupled to an output of the edge detector and an output coupled to the data input of the programmable logic array; and
a second multiplexer having an output coupled to an input of the edge detector and to a second input of the first multiplexer.
2. The integrated circuit of claim 1 , wherein the signal conditioner includes a synchronizer coupled between the input of the signal conditioner and a first input of the second multiplexer.
3. The integrated circuit of claim 2 , wherein the second multiplexer includes a second input coupled to the input of the signal conditioner.
4. The integrated circuit of claim 3 , wherein the signal conditioner includes a filter coupled between the synchronizer and the first input of the second multiplexer.
5. The integrated circuit of claim 4 , wherein the filter is a programmable filter configured to filter out signals having feature lengths shorter than a threshold.
6. The integrated circuit of claim 3 , wherein the signal conditioner includes a filter coupled between the input of the signal conditioner and a third input of the second multiplexer.
7. The integrated circuit of claim 2 , comprising a clock generator configured to generate a clock signal for the programmable logic array.
8. The integrated circuit of claim 2 , wherein the edge detector includes a clock input configured to receive a clock signal.
9. The integrated circuit of claim 8 , wherein the edge detector is configured to output a pulse having a duration equal to a period of the clock signal responsive to detecting a signal edge at the output of the second multiplexer.
10. The integrated circuit of claim 9 , wherein the edge is a rising edge.
11. The integrated circuit of claim 9 , wherein the edge is a falling edge.
12. A system-on-chip, comprising:
a signal conditioner including:
an input terminal;
a synchronizer having an input coupled to the input terminal;
a filter having an input coupled to an output of the synchronizer;
a first multiplexer having a first input coupled to the input terminal and a second input coupled to an output of the filter;
an edge detector having an input coupled to an output of the first multiplexer; and
a second multiplexer having a first input coupled to the output of the first multiplexer and a second input coupled to an output of the edge detector.
13. The system-on-chip of claim 12 , comprising a programmable logic array having a data input coupled to an output of the second multiplexer.
14. The system-on-chip of claim 13 , wherein the edge detector includes a clock input terminal that receives a clock signal of the programmable logic array.
15. The system-on-chip of claim 14 , wherein the programmable logic array includes a plurality of programmable logic elements, wherein at least one of the programmable logic elements is coupled to the data input.
16. The system-on-chip of claim 14 , comprising an input pad coupled to the input terminal of the signal conditioner.
17. The system-on-chip of claim 14 , comprising a sub-system including a data output coupled to the input terminal of the signal conditioner.
18. A method, comprising:
receiving a signal at an input of an edge detector and at a first input of a first multiplexer;
generating, with the edge detector, a pulse responsive to detecting an edge of the signal;
outputting the pulse to a second input of the first multiplexer;
outputting either the signal or the pulse from the first multiplexer to a data input of a programmable logic array;
receiving the signal at an input of a synchronizer and at a first input of a second multiplexer;
outputting the signal from the synchronizer to an input of a filter;
outputting the signal from the filter to a second input of the second multiplexer; and
outputting the signal from the second multiplexer to the edge detector and to the first input of the first multiplexer.
19. The method of claim 18 , comprising:
generating a clock signal;
operating the programmable logic array in accordance with the clock signal;
passing the clock signal to a clock terminal of the edge detector; and
generating the pulse with a duration corresponding to a period of the clock signal.