IP Library › Granted Patent US 11,982,987
Granted Patent B2
US 11,982,987 · App. 17/126,209 · Granted May 14, 2024

Programmable logic controller and analyzer

Inventor: Tetsuya Miyasaka (Osaka, JP)
Assignee: KEYENCE CORPORATION
G05B19/058G05B19/056G06F18/2413G05B2219/14107
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Quick Facts
Patent No.
US 11,982,987
App. No.
17/126,209
Granted
May 14, 2024
Kind
B2
Abstract

An object of the present invention is to efficiently identify an abnormal device by analyzing and classifying characteristics such as periodicity and continuity of data related to each device. A programmable logic controller collects data held by a device as a collection target out of the plurality of devices in accordance with a predetermined collection setting for each scan cycle of the user program, classifies each of the devices into one of a plurality of types on the basis of a characteristic of the collected time-series data of each of the devices, and determines a detection algorithm used in identification of the device as an abnormal device in accordance with the time-series data of the device collected by the collection section and the type of the device classified by the classification section for each of the devices.

Claims (59)

1. A programmable logic controller comprising:

an execution engine that repeatedly executes a user program;

a device memory having a plurality of devices that are storage areas for storing data accessed by the execution engine in accordance with the user program;

a collection section for collecting data held by a device as a collection target out of the plurality of devices in accordance with a predetermined collection setting for each execution cycle of the user program;

a classification section for classifying each of the devices into one of a plurality of types on a basis of a characteristic of time-series data of each of the devices collected by the collection section;

a determination section for determining a detection algorithm used in identification of the device as an abnormal device in accordance with the time-series data of the device collected by the collection section and the type of the device classified by the classification section for each of the devices; and

an identification section for identifying an abnormal device by analyzing the time-series data of the device collected by the collection section by using the detection algorithm determined by the determination section for the device in accordance with the type of the device classified by the classification section, wherein

the type includes at least two types out of a type taking a constant value, a type in which a value changes in a steady pattern in synchronization with an operation cycle of the programmable logic controller, a device in which a value changes in a steady pattern in synchronization with a cycle different from the operation cycle, a type in which a value changes irregularly, a type with an analog value, and a type in which a value increases monotonically or decreases monotonically.

2. The programmable logic controller according to claim 1 , wherein the identification section further identifies an abnormal device by analyzing a deviation between the time-series data of each of the devices collected by the collection section and time-series data at a normal time by using the detection algorithm determined by the determination section in accordance with a user instruction or periodically.

3. The programmable logic controller according to claim 1 , wherein

when the collection section accumulates series of time-series data of a predetermined number of scan cycles, the classification section classifies each of the series of time-series data on a basis of a characteristic of each of the series of time-series data, and

the determination section determines and updates the detection algorithm used in identification of an abnormality in accordance with the series of time-series data classified by the classification section.

4. The programmable logic controller according to claim 1 , wherein upon reception of a user instruction for an arbitrary device, the classification section classifies the device in accordance with the user instruction.

5. The programmable logic controller according to claim 1 , wherein when a value collected in a previous scan cycle and a value collected in a current scan cycle in a group of one or more devices have not changed in all the devices of the group as a collection target, the collection section deletes the value collected in the current scan cycle and compresses the collected time-series data.

6. The programmable logic controller according to claim 1 , wherein the determination section excludes time-series data classified by the classification section as the device in which a value changes irregularly, to determine a detection algorithm used in identification of an abnormality.

7. The programmable logic controller according to claim 1 , wherein the identification section identifies an abnormal device by performing analysis, using an evaluation variable used for analysis of the abnormal device and a parameter corresponding to the evaluation variable on a basis of a type of the time-series data classified by the classification section as the detection algorithm.

8. The programmable logic controller according to claim 7 , further comprising an additional learning determination section for determining whether a condition for additional learning has been satisfied,

wherein when the additional learning determination section determines that the condition for additional learning has been satisfied,

the classification section reclassifies each of the devices into one of a plurality of types on a basis of the type of each of the devices at present and a characteristic of time-series data of each of the devices collected by the collection section during a target period for additional learning, and

the determination section redetermines the detection algorithm used in identification of the device as an abnormal device in accordance with the time-series data of the device collected by the collection section for each of the devices during the target period for additional learning and the type of the device reclassified by the classification section or the detection algorithm of each of the devices at present.

9. The programmable logic controller according to claim 1 , wherein the identification section compares the detection algorithm determined by the determination section with a characteristic of time-series data corresponding to the detection algorithm and performs the identification as an abnormal device when a difference exceeds a predetermined threshold.

10. The programmable logic controller according to claim 1 , wherein

the determination section determines a time difference between change points of respective values in two series of time-series data as a detection algorithm used in identification of an abnormality, and

the identification section identifies two devices corresponding to the two series of time-series data as abnormal devices when the time difference in the two series of time-series data is out of a predetermined range.

11. The programmable logic controller according to claim 1 , further comprising an output section for outputting, as an identification result, a candidate device having a possibility of abnormality in a distinguishable manner.

12. The programmable logic controller according to claim 11 , wherein the output section displays, as the identification result, each of the devices on a display part in order of an abnormality degree indicating a size of the abnormality or in order of an occurrence time of the abnormality.

13. The programmable logic controller according to claim 11 , wherein the output section displays, as the identification result, time-series data at a normal time of the device identified as an abnormal device and time-series data at a time of abnormality on the display part in a comparable manner.

14. The programmable logic controller according to claim 1 , wherein the time-series data collected by the collection section includes image data.

15. The programmable logic controller according to claim 1 , wherein a characteristic of the time-series data is a characteristic related to periodicity or continuity.

16. The programmable logic controller according to claim 1 , further comprising:

a basic unit; and

an extension unit connected to the basic unit,

wherein the basic unit includes the execution engine, the device memory, and the collection section, and

the extension unit includes the classification section, the determination section, and the identification section.

17. The programmable logic controller according to claim 1 , further comprising:

a setting section for setting a monitoring cycle of the device;

a generation section for generating a monitoring start signal that starts monitoring for each monitoring cycle set by the setting section; and

an analysis section for analyzing time-series data to be analyzed in accordance with the monitoring start signal generated by the generation section by using the time-series data to be analyzed and the detection algorithm determined by the determination section out of the devices collected by the collection section, and for outputting the analysis result to the display part.

18. The programmable logic controller according to claim 1 , further comprising a memory card that temporarily holds the time-series data of the device collected by the collection section before the time-series data is used by the classification section and the identification section.

19. An analyzer communicatively connected to a programmable logic controller including

an execution engine that repeatedly executes a user program,

a device memory having a plurality of devices that are storage areas for storing data accessed by the execution engine in accordance with the user program, and

a collection section for collecting data held by a device as a collection target out of the plurality of devices in accordance with a predetermined collection setting for each scan cycle of the user program,

the analyzer comprising:

an acquisition section for acquiring time-series data of each of the devices collected by the collection section from the programmable logic controller;

a classification section for classifying each of the devices into one of a plurality of types on a basis of a characteristic of time-series data of each of the devices acquired by the collection section;

a determination section for determining a detection algorithm used in identification of the device as an abnormal device in accordance with the time-series data of the device collected by the collection section and the type of the device classified by the classification section for each of the devices;

an identification section for identifying an abnormal device by analyzing the time-series data of the device collected by the collection section by using the detection algorithm determined by the determination section for the device in accordance with the type of the device classified by the classification section; and

an output section for outputting a result of the identification by the identification section wherein

the type includes at least two types out of a type taking a constant value, a type in which a value changes in a steady pattern in synchronization with an operation cycle of the programmable logic controller, a device in which a value changes in a steady pattern in synchronization with a cycle different from the operation cycle, a type in which a value changes irregularly, a type with an analog value, and a type in which a value increases monotonically or decreases monotonically.

20. A programmable logic controller comprising:

an execution engine that repeatedly executes a user program;

a device memory having a plurality of devices that are storage areas for storing data accessed by the execution engine in accordance with the user program;

a collection section for collecting data held by a device as a collection target out of the plurality of devices in accordance with a predetermined collection setting for each execution cycle of the user program;

a classification section for classifying each of the devices into one of a plurality of types on a basis of a characteristic of time-series data of each of the devices collected by the collection section;

a determination section for determining a detection algorithm used in identification of the device as an abnormal device in accordance with the time-series data of the device collected by the collection section and the type of the device classified by the classification section for each of the devices; and

an identification section for identifying an abnormal device by analyzing the time-series data of the device collected by the collection section by using the detection algorithm determined by the determination section for the device in accordance with the type of the device classified by the classification section, wherein

the determination section determines a time difference between change points of respective values in two series of time-series data as a detection algorithm used in identification of an abnormality, and

the identification section identifies two devices corresponding to the two series of time-series data as abnormal devices when the time difference in the two series of time-series data is out of a predetermined range.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2020
From: MIYASAKA, TETSUYA
To: KEYENCE CORPORATION
Reel/Frame 054689/0461 →
Priority Claims (2)
JP 2020-014970 · Jan 31, 2020 · national
JP 2020-161926 · Sep 28, 2020 · national
Continuity (1)
Related Publication 20210240154A1 · Aug 5, 2021