Methods and apparatus for constructing digital circuits for performing matrix operations
Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is very computationally intensive field. Fortunately, many of the required calculations can be performed in parallel such that specialized processors can greatly increase computation performance. In particular, Graphics Processor Units (GPUs) are often used in artificial intelligence. Although GPUs have helped, they are not ideal for artificial intelligence. Specifically, GPUs are used to compute matrix operations in one direction with a pipelined architecture. However, artificial intelligence is a field that uses both forward propagation computations and back propagation calculations. To efficiently perform artificial intelligence calculations, a symmetric matrix processing element is introduced. The symmetric matrix processing element can perform forward propagation and backward propagation calculations just as easily. Furthermore, both of these calculations can be performed without reloading weight matrix values.
1. A method of digitally performing matrix operations in a single digital processing circuit, said method comprising:
performing forward propagation calculations by:
reading a row of matrix weight data from a memory circuit;
multiplying said row of matrix weight data with an input vector in a plurality of parallel arithmetic logic units to produce an output vector; and
storing said output vector in result register file; and
performing back propagation calculations by:
reading a row of matrix data from said memory circuit;
independently multiplying said row of matrix data with a delta output error vector in a plurality of parallel arithmetic logic units and accumulating partial results to produce a delta input vector; and
storing said delta input vector in said result register file.
2. The method of digitally performing matrix operations as set forth in claim 1 , said method further comprising:
reducing said output vector in said result register file with a reduction tree circuit.
3. The method of digitally performing matrix operations as set forth in claim 2 wherein said reduction tree circuit creates a sum of values in said result register file.
4. The method of digitally performing matrix operations as set forth in claim 2 wherein said reduction tree circuit creates a set of sums from values in said result register file.
5. The method of digitally performing matrix operations as set forth in claim 1 , said method further comprising:
performing weight matrix updates by:
loading a row of input data into an operand register;
reading said row of matrix data from said memory circuit,
reading a row of output error delta data;
independently multiplying said row of input data with said row of output error delta data in a plurality of parallel arithmetic logic units and accumulating multiplication results to said row of matrix data; and
storing said row of matrix data back to said memory circuit.
6. The method of digitally performing matrix operations as set forth in claim 1 wherein said result register file stores multiple different sets of result data values.
7. The method of digitally performing matrix operations as set forth in claim 1 wherein said single digital processing circuit processes 8-bit integer values.
8. The method of digitally performing matrix operations as set forth in claim 1 wherein said single digital processing circuit processes 16-bit floating point values.
9. The method of digitally performing matrix operations as set forth in claim 1 wherein said single digital processing circuit processes 32-bit floating point values.
10. The method of digitally performing matrix operations as set forth in claim 1 wherein a control system further updates said row of matrix weight data using a read, modify, write operation.