Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices
A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
1. A method, comprising:
identifying a first wordline connected to a plurality of groups of first memory cells based on a determination that data bits represented by threshold voltages of the first memory cells and determined in a read operation have a bit error rate above a threshold;
storing first data items as independent first codewords of an error correction code technique into a first portion of the first memory cells, wherein the first codewords have a same length;
generating second data items as redundant information from the first codewords;
storing the second data items in a second portion of the first memory cells; and
in response to a determination that the bit error rate becomes lower than the threshold, storing third data items as independent second codewords of the same length in the first portion of the first memory cells and the second portion of the first memory cells.
2. The method of claim 1 , wherein each of the second data item is generated from a subset of the first codewords.
3. The method of claim 2 , wherein each of the second data item is generated from an XOR operation applied on the subset of the first codewords.
4. The method of claim 3 , wherein at least a portion of the subset of the first codewords is distributed across different page types.
5. The method of claim 4 , wherein at least a portion of the subset of the first codewords is distributed across different planes.
6. The method of claim 2 , wherein each of the second data item is generated from an XNOR operation applied on the subset of the first codewords.
7. The method of claim 1 , further comprising:
identifying a second wordline connected to a plurality of groups of second memory cells based on a determination that data bits represented by threshold voltages of the second memory cells and determined in a read operation have a bit error rate below the threshold; and
storing third data items as independent third codewords into the second memory cells, without generating redundant information from the third codewords for storing into the second memory cells, wherein the third codewords have the same length as the first codewords.
8. A memory sub-system, comprising:
a processing device; and
an integrated circuit die having a first wordline and a plurality of groups of first memory cells connected to the first wordline;
wherein in response to a determination that data bits represented by threshold voltages of the first memory cells and determined in a read operation have a bit error rate above a threshold, the processing device is configured to:
store first data items as independent first codewords of an error correction code technique into a first portion of the first memory cells, wherein the first codewords have a same length;
generate second data items as redundant information from the first codewords; and
store the second data items in a second portion of the first memory cells; and
wherein in response to a determination that the bit error rate becomes lower than the threshold, the processing device is configured to store third data items as independent second codewords of the same length in the first portion of the first memory cells and the second portion of the first memory cells.
9. The memory sub-system of claim 8 , wherein each of the second data item is generated from a subset of the first codewords.
10. The memory sub-system of claim 9 , wherein each of the second data item is generated from an XOR operation, or an XNOR operation, applied on the subset of the first codewords.
11. The memory sub-system of claim 10 , wherein at least a portion of the subset of the first codewords is distributed across different page types.
12. The memory sub-system of claim 11 , wherein at least a portion of the subset of the first codewords is distributed across different planes.
13. The memory sub-system of claim 8 , wherein the integrated circuit die further has a second wordline and a plurality of groups of second memory cells connected to the second wordline; and in response to a determination that data bits represented by threshold voltages of the second memory cells and determined in a read operation have a bit error rate below the threshold, the processing device is further configured to store third data items as independent third codewords into the second memory cells, without generating redundant information from the third codewords for storing into the second memory cells, wherein the third codewords have the same length as the first codewords.
14. A non-transitory computer storage medium storing instructions which, when executed on a computing device, cause the computing device to perform a method, comprising:
identifying a first wordline connected to a plurality of groups of first memory cells based on a determination that data bits represented by threshold voltages of the first memory cells and determined in a read operation have a bit error rate above a threshold;
storing first data items as independent first codewords of an error correction code technique into a first portion of the first memory cells, wherein the first codewords have a same length;
generating second data items as redundant information from the first codewords;
storing the second data items in a second portion of the first memory cells; and
in response to a determination that the bit error rate becomes lower than the threshold, storing third data items as independent second codewords of the same length in the first portion of the first memory cells and the second portion of the first memory cells.
15. The non-transitory computer storage medium of claim 14 , wherein each of the second data item is generated from a subset of the first codewords.
16. The non-transitory computer storage medium of claim 15 , wherein each of the second data item is generated from an XOR operation applied on the subset of the first codewords.
17. The non-transitory computer storage medium of claim 16 , wherein at least a portion of the subset of the first codewords is distributed across different page types.
18. The non-transitory computer storage medium of claim 17 , wherein at least a portion of the subset of the first codewords is distributed across different planes.
19. The non-transitory computer storage medium of claim 15 , wherein each of the second data item is generated from an XNOR operation applied on the subset of the first codewords.
20. The non-transitory computer storage medium of claim 14 , wherein the method further comprises:
identifying a second wordline connected to a plurality of groups of second memory cells based on a determination that data bits represented by threshold voltages of the second memory cells and determined in a read operation have a bit error rate below the threshold; and
storing third data items as independent third codewords into the second memory cells, without generating redundant information from the third codewords for storing into the second memory cells, wherein the third codewords have the same length as the first codewords.