IP Library › Granted Patent US 11,988,720
Granted Patent B2
US 11,988,720 · App. 17/312,475 · Granted May 21, 2024

Semiconductor device and battery pack

Inventors: Kei Takahashi (Isehara, JP); Takayuki Ikeda (Atsugi, JP); Ryota Tajima (Isehara, JP); Mayumi Mikami (Atsugi, JP); Yohei Momma (Isehara, JP); Munehiro Kozuma (Atsugi, JP); Takanori Matsuzaki (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G01R31/392H01M10/44H01M10/48H02J7/005H01L29/7869H01M2220/20
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Quick Facts
Patent No.
US 11,988,720
App. No.
17/312,475
Granted
May 21, 2024
Kind
B2
Abstract

A semiconductor device that detects deterioration of a secondary battery is provided. The semiconductor device includes a power gauge, an anomalous current detection circuit, and a control circuit. The power gauge includes a current divider circuit and an integrator circuit. The anomalous current detection circuit includes a first memory, a second memory, and a first comparator. The integrator circuit can convert a detection current detected at the current divider circuit into a detection voltage by integrating the detection current. The anomalous current detection circuit is supplied with the detection voltage, a first signal at a first time, and a second signal at a second time. The first signal can make the detection voltage at the first time be stored in the first memory and the second signal can make the detection voltage at the second time be stored in the second memory. The first comparator outputs a change from the detection voltage at the first time to the detection voltage at the second time as a first output signal to the control circuit.

Claims (29)

1. A semiconductor device comprising a first circuit and a second circuit,

wherein the first circuit comprises a power gauge and an anomalous current detection circuit,

wherein the power gauge comprises a current divider circuit and an integrator circuit,

wherein the anomalous current detection circuit comprises a first memory, a second memory, and a first comparator,

wherein the integrator circuit is configured to convert a detection current detected at the current divider circuit into a detection voltage by integrating the detection current,

wherein the anomalous current detection circuit is configured to be supplied with the detection voltage, a first signal at a first time, and a second signal at a second time,

wherein the anomalous current detection circuit is configured to store the detection voltage at the first time in the first memory using the first signal,

wherein the anomalous current detection circuit is configured to store the detection voltage at the second time in the second memory using the second signal, and

wherein the first comparator is configured to output a change from the detection voltage at the first time to the detection voltage at the second time as a first output signal to the second circuit.

2. The semiconductor device according to claim 1 ,

wherein the first comparator is configured to output the first output signal to the second circuit when the detection voltage stored in the first memory is larger than the detection voltage stored in the second memory, and

wherein the first comparator is configured to invert the first output signal to output it to the second circuit when the detection voltage stored in the second memory is larger than the detection voltage stored in the first memory.

3. The semiconductor device according to claim 1 ,

wherein the power gauge comprises a second comparator having a hysteresis property,

wherein the second comparator is configured to judge the detection voltage using a first judge voltage and a second judge voltage,

wherein an output signal of the second comparator is configured to invert an output polarity of the current divider circuit when the detection voltage is smaller than the first judge voltage,

wherein the output signal of the second comparator is configured to invert the output polarity of the current divider circuit when the detection voltage is larger than the second judge voltage, and

wherein the output signal of the second comparator is output to the second circuit.

4. The semiconductor device according to claim 3 , wherein the second circuit is configured to generate the first signal and the second signal from the output signal of the second comparator.

5. The semiconductor device according to claim 3 ,

wherein the second circuit is configured to set a predetermined time, and

wherein the second circuit is configured to output the first signal or the second signal after the predetermined time from a change moment of the output signal of the second comparator.

6. The semiconductor device according to claim 1 , wherein the second circuit is one of a control circuit and a processor.

7. The semiconductor device according to claim 1 ,

wherein the semiconductor device comprises a transistor, and

wherein the transistor comprises an oxide semiconductor in its channel formation region.

8. A battery pack comprising:

the semiconductor device according to claim 1 , provided over a flexible substrate, and

a secondary battery.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2021
From: TAKAHASHI, KEI; IKEDA, TAKAYUKI; TAJIMA, RYOTA; MIKAMI, MAYUMI; MOMMA, YOHEI; KOZUMA, MUNEHIRO; MATSUZAKI, TAKANORI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 056504/0358 →
Priority Claims (2)
JP 2018-238529 · Dec 20, 2018 · national
JP 2019-123810 · Jul 2, 2019 · national
Continuity (1)
Related Publication 20220052387A1 · Feb 17, 2022