Method for CXL fallback in a CXL system
An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.
1. An information handling system, comprising:
a processor; and
a compute express link (CXL) device coupled to the processor by a peripheral component interface-express (PCIe)/CXL link;
wherein the processor is configured to initiate a link training on the PCIe/CXL link, to determine that the PCIe/CXL link failed to train to a first data rate, to train the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and to operate the CXL device in a PCIe mode in response to training the PCIe/CXL link to the second data rate.
2. The information handling system of claim 1 , wherein the first data rate includes a first signaling rate of the PCIe/CXL link and the second data rate includes a second signaling rate of the PCIe/CXL link, and wherein the second signaling rate is lower than the first signaling rate.
3. The information handling system of claim 2 , wherein the first signaling rate is greater than or equal to eight (8) giga-transfers per seconds (GT/s).
4. The information handling system of claim 3 , wherein the second signaling rate is less than eight (8) GT/s.
5. The information handling system of claim 2 , wherein the first data rate includes a first link width of the PCIe/CXL link and the second data rate includes a second link width of the CXL/PCIe link, and wherein the second link width is lower than the first link width.
6. The information handling system of claim 5 , wherein the first link width includes 16 lanes, and wherein the second link width includes 8 lanes.
7. The information handling system of claim 1 , wherein the first data rate includes a first link width of the PCIe/CXL link and the second data rate includes a second link width of the CCXL/PCIe link, and wherein the second link width is lower than the first link width.
8. The information handling system of claim 7 , wherein the first link width includes 16 lanes, and wherein the second link width includes 8 lanes.
9. The information handling system of claim 1 , wherein in initiating the link training on the PCIe/CXL link, the processor is further configured to initiate a Link Training and Status State Machine (LTSSM) block to check each lane of the PCIe link.
10. The information handling system of claim 1 , wherein in response to operating the CXL device in the CXL mode, the processor is further configured to report an error in training the PCIe/CXL link.
11. A method, comprising:
coupling a compute express link (CXL) device of an information handling system to a processor of the information handling system by a peripheral component interface-express (PCIe)/CXL link;
initiating, by the processor, a link training on the PCIe/CXL link;
determining that the PCIe/CXL link failed to train to a first data rate;
training the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate; and
operating the CXL device in a PCIe mode in response to training the PCIe/CXL link to the second data rate.
12. The method of claim 11 , wherein the first data rate includes a first signaling rate of the PCIe/CXL link and the second data rate includes a second signaling rate of the PCIe/CXL link, and wherein the second signaling rate is lower than the first signaling rate.
13. The method of claim 12 , wherein the first signaling rate is greater than or equal to eight (8) giga-transfers per seconds (GT/s).
14. The method of claim 13 , wherein the second signaling rate is less than eight (8) GT/s.
15. The method of claim 12 , wherein the first data rate includes a first link width of the PCIe/CXL link and the second data rate includes a second link width of the CXL/PCIe link, and wherein the second link width is lower than the first link width.
16. The method of claim 15 , wherein the first link width includes 16 lanes, and wherein the second link width includes 8 lanes.
17. The method of claim 11 , wherein the first data rate includes a first link width of the PCIe/CXL link and the second data rate includes a second link width of the CXL/PCIe link, and wherein the second link width is lower than the first link width.
18. The method of claim 17 , wherein the first link width includes 16 lanes, and wherein the second link width includes 8 lanes.
19. The method of claim 11 , wherein in initiating the link training on the PCIe/CXL link, the method further comprises initiating a Link Training and Status State Machine (LTSSM) block to check each lane of the PCIe link.
20. An information handling system, comprising:
a processor; and
a compute express link (CXL) device coupled to the processor by a peripheral component interface-express (PCIe)/CXL link;
wherein the processor is configured to initiate a link training on the PCIe/CXL link, to determine that the PCIe/CXL link failed to train to a first data rate, to train the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, to operate the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate, and to report an error in training the PCIe/CXL link in response to operating the CXL device in the PCIe mode, wherein the first data rate includes a first signaling rate of the PCIe/CXL link and the second data rate includes a second signaling rate of the PCIe/CXL link, and wherein the second signaling rate is lower than the first signaling rate.