Memory module with persistent calibration

1. A memory module comprising:

one or more memory devices;

a memory interface chip coupled to the one or more memory devices via one or more internal communication links, the one or more internal communication links comprising a shared command/address line coupled between the memory interface chip and each of the one or more memory devices and one or more respective data lines coupled between the memory interface chip and each respective memory device; and

a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more internal communication links, the one or more sets of training and calibration settings comprising a first set of training and calibration settings corresponding to the shared command/address line and a second set of training and calibration settings corresponding to the one or more respective data lines, wherein the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and used to configure one or more components of the memory interface chip during the operation of the memory module.

2. The memory module of claim 1 , wherein the one or more sets of training and calibration settings are stored in the persistent memory during manufacturing and assembly of the memory module.

3. The memory module of claim 1 , wherein the memory interface chip is to couple the memory module to an external host system, and wherein the memory interface chip is to isolate the one or more internal communication links from the external host system.

4. The memory module of claim 1 , wherein the one or more memory devices comprise dynamic random access memory (DRAM) devices.

5. The memory module of claim 1 , wherein memory interface chip comprises control logic to:

detect a power-on event for the memory module;

receive an indication of operating conditions for the memory module;

retrieve at least one of the one or more sets of training and calibration settings corresponding to the operating conditions from the persistent memory; and

apply the at least one of the one or more sets of training and calibration settings to transmitter and receiver circuits of the memory interface chip.

6. The memory module of claim 1 , wherein the persistent memory is disposed on the memory interface chip.

7. A memory interface chip comprising:

a persistent memory; and

control logic coupled to the persistent memory, wherein the control logic is to retrieve a set of training and calibration settings from the persistent memory, wherein the set of training and calibration settings is stored in the persistent memory before operation of the memory interface chip, and to apply the set of training and calibration settings to components of the memory interface chip during operation of one or more internal communication links coupled between the memory interface chip and one or more memory devices, the one or more internal communication links comprising a shared command/address line coupled between the memory interface chip and each of the one or more memory devices and one or more respective data lines coupled between the memory interface chip and each respective memory device, and wherein the set of training and calibration settings comprises a first set of training and calibration settings corresponding to the shared command/address line and a second set of training and calibration settings corresponding to the one or more respective data lines.

8. The memory interface chip of claim 7 , wherein the set of training and calibration settings is one of a plurality of sets of training and calibration settings stored in the persistent memory during manufacturing and assembly of a memory module.

9. The memory interface chip of claim 8 , wherein the memory interface chip is to couple the memory module to an external host system, and wherein the memory interface chip is to isolate the one or more internal communication links from the external host system.

10. The memory interface chip of claim 7 , wherein the one or more memory devices comprise dynamic random access memory (DRAM) devices.

11. The memory interface chip of claim 8 , wherein the control logic is further to:

detect a power-on event for the memory module;

receive an indication of operating conditions for the memory module; and

determine that the set of training and calibration settings corresponds to the operating conditions from the persistent memory.

12. A method of operation of a memory interface chip in a memory module, the method comprising:

detecting a power-on event for the memory module;

receiving an indication of operating conditions for the memory module;

retrieving at least one set of training and calibration settings corresponding to the operating conditions from a persistent memory in the memory module, wherein the at least one set of training and calibration settings are stored in the persistent memory before operation of the memory module; and

applying the at least one set of training and calibration settings to components of the memory interface chip during operation of one or more internal communication links coupled between the memory interface chip and one or more memory devices in the memory module, the one or more internal communication links comprising a shared command/address line coupled between the memory interface chip and each of the one or more memory devices and one or more respective data lines coupled between the memory interface chip and each respective memory device, and wherein the at least one set of training and calibration settings comprises a first set of training and calibration settings corresponding to the shared command/address line and a second set of training and calibration settings corresponding to the one or more respective data lines.

13. The method of claim 12 , wherein the at least one set of training and calibration settings is one of a plurality of sets of training and calibration settings stored in the persistent memory during manufacturing and assembly of a memory module.

14. The method of claim 13 , wherein the memory interface chip is to couple the memory module to an external host system, and wherein the memory interface chip is to isolate the one or more internal communication links from the external host system.