Neuromorphic apparatus having 3D stacked synaptic structure and memory device having the same

1. A synaptic module of a neuromorphic apparatus having a three-dimensionally-stacked synaptic structure, the synaptic module comprising:

a first word line;

a first memory cell comprising a first metal disposed on the first word line, a ferroelectric disposed on the first metal, an insulator disposed on the ferroelectric, and a second metal disposed on the insulator;

a bit line is disposed on the second metal of the first memory cell;

a second memory cell comprising a second metal disposed on the bit line, an insulator disposed on the second metal of the second memory cell, a ferroelectric disposed on the insulator of the second memory cell, and a first metal disposed on the ferroelectric of the second memory cell; and

a second word line is disposed on the first metal of the second memory cell,

wherein the second metal, the insulator, the ferroelectric, and the first metal of the second memory cell are arranged sequentially in a direction from the bit line to the second word line, in an order of the second metal, the insulator, the ferroelectric, and the first metal.

2. A synaptic module of a neuromorphic apparatus having a three-dimensionally-stacked synaptic structure, the synaptic module comprising:

a first word line;

a first memory cell comprising a first metal disposed on the first word line, a ferroelectric disposed on the first metal, an insulator disposed on the ferroelectric, and a second metal disposed on the insulator;

a bit line is disposed on the second metal of the first memory cell;

a second memory cell comprising a second metal disposed on the bit line, an insulator disposed on the second metal of the second memory cell, a ferroelectric disposed on the insulator of the second memory cell, and a first metal disposed on the ferroelectric of the second memory cell; and

a second word line is disposed on the first metal of the second memory cell,

wherein a first potential barrier height between the second metal and the insulator is greater than a second potential barrier height between the first metal and the ferroelectric.

3. A synaptic module of a neuromorphic apparatus having a three-dimensionally-stacked synaptic structure, the synaptic module comprising:

a first word line;

a first memory cell comprising a first metal disposed on the first word line, a ferroelectric disposed on the first metal, an insulator disposed on the ferroelectric, and a second metal disposed on the insulator;

a bit line is disposed on the second metal of the first memory cell;

a second memory cell comprising a second metal disposed on the bit line, an insulator disposed on the second metal of the second memory cell, a ferroelectric disposed on the insulator of the second memory cell, and a first metal disposed on the ferroelectric of the second memory cell; and

a second word line is disposed on the first metal of the second memory cell,

wherein a first dielectric constant of the insulator is less than a second dielectric constant of the ferroelectric.

4. The synaptic module of claim 1 , wherein the neuromorphic apparatus comprises a plurality of unit synaptic modules,

wherein each of the plurality of unit synaptic modules comprises a first synaptic module having a structure of the synaptic module, a first decoder for selecting one of the plurality of unit synaptic modules, and a second synaptic module having the structure of the synaptic module, and

wherein the first decoder is interposed between the first synaptic module and the second synaptic module.

5. The synaptic module of claim 1 , wherein the bit line corresponds to an axon of a neural network, and

the first word line and the second word line respectively correspond to dendrites of the neural network.

6. The synaptic module of claim 1 , wherein the first metal is one selected from a group consisting of TiN, Al, Zr, La, Y, Ti, and W,

wherein the second metal is one selected from a group consisting of TiN, Al, Zr, La, Y, Ti, and W,

wherein the insulator is one selected from a group consisting of Al 2 O 3 , SiO 2 , and Si 3 N 4 , and

wherein the ferroelectric is HfO doped with any one or any combination of Si, Zr, Y, Al, Gd, Sr, and La.

7. An unit synaptic module of a neuromorphic apparatus having a three-dimensionally-stacked synaptic structure, the unit synaptic module comprising:

a first synaptic layer and a second synaptic layer disposed on the first synaptic layer, wherein the first synaptic layer and the second synaptic layer having a stack structure of the synaptic module according to claim 1 ;

a third synaptic layer and a fourth synaptic layer disposed on the third synaptic layer, wherein the third synaptic layer and the fourth synaptic layer having a stack structure of the synaptic module according to claim 1 ; and

a first decoder interposed between the second synaptic layer and the third synaptic layer.

8. A neuromorphic apparatus comprising a three-dimensionally-stacked synaptic structure, the neuromorphic apparatus comprising:

a plurality of unit synaptic modules, each of the plurality of unit synaptic modules corresponding to the unit synaptic module according to claim 7 ;

a second decoder that provides a level selection signal to the first decoder included in one among the plurality of unit synaptic modules to be accessed; and

a third decoder that generates an address of one among a plurality of memristers to be accessed in a memrister array of one among the plurality of synaptic layers included in the one among the plurality of unit synaptic modules to be accessed,

wherein, in each of the plurality of unit synaptic modules, neighboring memristers included in neighboring synaptic layers have a plurality of stack structures symmetrical to each other.

9. A memory device having a three-dimensionally-stacked synaptic structure, the memory device comprising:

a plurality of unit memory modules, each of the plurality of unit memory modules corresponding to the unit synaptic module according to claim 7 ;

a second decoder that provides a level selection signal to the first decoder included in one among the plurality of unit memory modules to be accessed; and

a third decoder that generates an address of one among a plurality of memory cells to be accessed in a memory cell array of one among a plurality of memory layers included in the one among the plurality of unit memory modules to be accessed,

wherein, in each of the plurality of unit memory modules, neighboring memory cells included in neighboring memory layers have a plurality of stack structures symmetrical to each other.