Neural processing unit capable of testing component therein during runtime

1. A neural processing unit (NPU) for testing a component of the NPU during runtime, the NPU comprising:

a plurality of functional components, each of the plurality of functional components including an electronic circuit;

at least one wrapper connected to at least one functional component of the plurality of functional components;

a field programmable gate array (FPGA); and

an in-system component tester (ICT) configured to:

select one of the at least one functional component, in an idle state, as a component under test (CUT), prepare or start a test, via the at least one wrapper, of the selected functional component,

stop the test, based on a detection of a collision due to an access to the selected functional component, and

complete the test, when no collision is detected,

wherein when the selected functional component is determined to be defective during the test, the FPGA is configured to imitate a normal function of the selected functional component.

2. The NPU of claim 1 , wherein the ICT is further configured to monitor states of the plurality of the functional components via the at least one wrapper.

3. The NPU of claim 1 , wherein the ICT is further configured to:

recover the at least one functional component according to the stop; or

return a connection of the selected functional component to the at least one wrapper according to the stop.

4. The NPU of claim 1 , wherein the ICT is further configured to perform again the selection if the selected functional component is in the idle state again after the stop.

5. The NPU of claim 1 , wherein the ICT is further configured to drive a back-off timer for the collision, and if the back-off timer for the collision has expired, to perform again the selection.

6. The NPU of claim 1 , wherein the plurality of functional components include at least one of:

at least one memory;

at least one controller; and

at least one array of processing elements.

7. The NPU of claim 6 , wherein the plurality of functional components further include at least one of a scheduler and an interface.

8. The NPU of claim 1 , wherein the ICT is further configured to instruct the at least one wrapper to isolate the selected functional component.

9. The NPU of claim 1 , wherein the ICT includes:

a detector configured to monitor states of the plurality of the functional components;

a scheduler configured to manage an operation of the ICT;

a generator configured to generate test input data; and

a tester configured to analyze a test result acquired from a CUT processing of the test input data.

10. The NPU of claim 9 , wherein the test input data includes predefined test data or random bit streams generated based on a seed.

11. The NPU of claim 1 , wherein the ICT is further configured to:

analyze a test result acquired from the selected functional component after the test is completed, the analyzed test result determining whether the selected functional component is normal or defective; and

return a connection of the selected functional component to the at least one wrapper if the analyzed test result determines the selected functional component to be normal.

12. The NPU of claim 11 ,

wherein the plurality of functional components include a spare component corresponding to the selected functional component analyzed as defective; and

wherein the ICT is further configured to activate the spare component if the analyzed test result determines the selected functional component to be defective.

13. The NPU of claim 11 , wherein the FPGA has an address that is revoked and replaced by an address of the selected functional component if the analyzed test result represents that the selected functional component is defective.

14. The NPU of claim 11 , wherein the ICT is further configured to deactivate the selected functional component if the analyzed test result determines the selected functional component to be defective.

15. The NPU of claim 14 , wherein the deactivation of the selected functional component is performed by revoking an address of the selected functional component.

16. The NPU of claim 14 , wherein the deactivation of the selected functional component is performed by powering off the selected functional component.

17. The NPU of claim 14 , wherein the deactivation of the selected functional component is performed by isolating or cutting off a supply of power to the selected functional component.

18. The NPU of claim 1 ,

wherein the CUT includes a plurality of flip-flops;

wherein the test includes a scan test different from a function test; and

wherein, for the scan test, the ICT is further configured to:

connect the plurality of flip-flops to each other,

apply a test input to at least one flip-flop of the plurality of flip-flops, and

acquire a test result from operations of combinational logics of the flip-flops to analyze whether the CUT is defective or normal during runtime.

19. A method for testing a component of a neural processing unit (NPU) during runtime, the method comprising:

selecting, among a plurality of functional components in the NPU, at least one functional component, which is in an idle state, as a component under test (CUT);

preparing or starting a test of the selected at least one functional component;

stopping the test, based on a detection of a collision due to an access to the selected functional component;

completing the test, when no collision is detected;

when the selected functional component is determined to be defective during the test, replacing the selected functional component with a field programmable gate array (FPGA); and

causing the FPGA to imitate a normal function of the selected functional component.